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Lead the design of Cerebras' next-generation AI chips, focusing on high-performance RTL development and integration while collaborating with cross-functional teams and external ASIC vendors.
Design and verify FPGA/ASIC digital circuits for aerospace/defense avionics, writing RTL in VHDL/Verilog and ensuring DO-254 compliance.
Design and verify mixed-signal ICs for current sensing, using RTL, SystemVerilog, VHDL, and UVM to ensure first-pass silicon success.
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing…
Design and implement high-performance FPGA logic for next-gen NAND Flash storage systems using Xilinx tools and RTL, while collaborating on embedded firmware and system validation.
The Apple design team is looking for an experienced engineer to develop multiple IPs for Apple SoCs (in Storage, Computer Vision and RISC-V CPU domains). In this Role you will get to handle micro-architecture…
Designs and verifies RTL IP blocks for networking solutions, collaborating with architects and physical design teams to ensure first-pass silicon success.
Design and implement high-performance RISC-V CPU cores, focusing on microarchitecture, RTL coding, and collaboration with verification and physical implementation teams.
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…
RESPONSIBILITIES Technical Leadership & Strategy (40%) Define and own the end-to-end chip design strategy, methodology, and technology roadmap across all design verticals — SoC, Analog, Digital, Product & Test…
Designs and drives the security architecture for FPGA, SoC, and ASIC products, focusing on hardware security, Root of Trust, secure boot, and cryptography to ensure resilient, compliant silicon solutions.
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and SystemVerilog.
Designs and implements next-gen SSD controller ASICs, writing RTL, collaborating on verification, and optimizing flows with AI-assisted tools.
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More…
Lead the design, testing, and integration of FPGA firmware for high-performance imaging systems, collaborating with hardware and software teams to meet manufacturing requirements.
Join Kyocera International, Inc. We’re hiring a Senior Principal Engineer Digital ASIC Design at our San Diego, CA facility! Salary Range: $214,000 - 348,000 annually (Final offer based on experience, education,…
Lead the architecture and RTL design of high-speed switching fabrics for next-gen memory and AI interconnects, guiding teams from spec to silicon bring-up.
Integrate RISC processors (RISC-V/Arm) into SoC platforms, configure subsystems, and collaborate on RTL, firmware, and system bring-up for Bitdeer’s Bitcoin mining and AI cloud hardware.
Principal Engineer leads verification strategy for next-gen UA Link Switch SoCs, using UVM/SystemVerilog to ensure first-silicon success for high-speed interconnect and memory subsystems.
Principal Design Engineer at Rambus to architect and implement next-gen PCIe IP in System Verilog, prototype on FPGAs, and collaborate with global teams.
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