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Principal Electrical Engineer verifies FPGA-based radar designs using SystemVerilog, UVM, and industry simulators, ensuring functional correctness and coverage for control/signal-processing applications.
Develop flight software for satellite optical inter-satellite links, including real-time control, fault tolerance, and AI-driven recovery, targeting embedded Linux and RTOS.
Leads hardware/software co-verification for SoC devices using emulators (e.g., Cadence Palladium) and FPGAs, bridging RTL porting, firmware development, and system-level testing across pre- and post-silicon phases.
Designs high-speed digital circuit boards for military radar systems using CAD tools, power/signal integrity analysis, and embedded processors; collaborates on FPGA-based designs and hardware testing.
Senior Electrical Engineer verifies FPGA-based radar designs using SystemVerilog/UVM testbenches and industry simulators, ensuring functional correctness and coverage.
Architect and lead validation of next-gen memory subsystems (DDR5, LPDDR5/6, HBM) for FPGAs, defining scalable methodologies and driving silicon bring-up, debug, and customer enablement.
Senior Embedded Firmware/Flight Software Engineer Psionic, Inc. is a startup focused on lidar sensors for autonomous systems. We value our customer relationships, our diverse and dynamic work environment, and our…
Lead verification of AMD’s IOHUB subsystem, defining test plans and closing coverage for high-performance interconnect IP used in CPUs, GPUs, and data-center hardware.
Principal Fabric/Network Architect designs the end-to-end data path for Neurophos’ optical AI accelerator, including RDMA transports, PCIe bridges, NICs, and HBM DMA, to scale distributed inference workloads.
Design and verify digital logic for novel AI hardware using SystemVerilog, collaborating across RTL, verification, and physical design to tape out custom ASICs.
Build and debug SystemVerilog/UVM testbenches for ASIC IP blocks powering 5G networks, from block-level to top-level verification and SW-driven validation.
Design and build confidential AI systems that run in trusted execution environments, ensuring model integrity and secure cloud-native deployment.
Design and validate next-gen telematics hardware and baseband systems for automotive OEMs, integrating cellular, GNSS, Wi-Fi, and Ethernet while ensuring automotive-grade reliability and compliance.
Design and build confidential AI systems that protect models and data using trusted execution environments, remote attestation, and secure provisioning in cloud-native and on-prem deployments.
Design and optimize FPGA-based hardware for ultra-low-latency trading infrastructure, integrating Ethernet stacks and custom logic to parse and route exchange data efficiently.
Tech Lead Design Engineer Location: San Jose, California, United States Department: Board Validation Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By…
Optical Validation Engineer, Principal Location: San Jose, California, United States Department: Optical Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By…
Hardware engineer optimizing NPU/SoC-based boards for edge AI devices, debugging power/interface issues, and supporting manufacturing ramp-up and customer deployments.
Develops BSP and system software for ARM/RISC-V SoCs running Linux, including board bring-up, firmware, and device drivers for edge AI NPUs.
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