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Designs and implements ultra-high-speed Ethernet test platforms using cutting-edge FPGAs, focusing on Layer 1–4 protocols and next-gen standards like 1.6Tbps Ethernet.
Leads the design and integration of digital subsystems for Automotive Ethernet PHY products, including PCS logic, safety mechanisms, and system-level validation in a semiconductor environment.
Design verification engineer building and running UVM/SystemVerilog testbenches for AR display ICs using Siemens Questa, plus coverage closure and automation in Linux.
Designs and verifies FPGA hardware using VHDL/Verilog/SystemVerilog, UVM testbenches, and Xilinx tools, while guiding a remote verification team on DO-254 processes.
Note: This position is posted for Markham, but it is open to candidates across Canada, including Mississauga, Nepean, and Ottawa. The role can be hybrid or fully remote depending on your location and preference. We Are…
Lead the design and integration of system-on-chip (SoC) logic and features using Verilog RTL, focusing on power, clock/reset domains, and interconnect protocols like AXI and PCIe.
Design engineer for MIPS S8200 AI CPU processor family: microarchitecture and verification. AI CPU Design Engineer About MIPS @ GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing…
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Design and verify integrated circuits for AR display systems, building UVM-based testbenches and using Siemens Questa for simulation and debug.
Design and verify next-gen high-speed networking switch silicon chips, collaborating with architecture and firmware teams to optimize throughput and latency.
Designs and integrates complex System-on-Chip (SOC) components for high-performance chips, collaborating with cross-functional teams to optimize RTL integration, chip build, and verification using SystemVerilog and scripting languages.
Designs and leads the development of high-performance microcontrollers and SoCs for edge AI applications, using Verilog/SystemVerilog, synthesis, and verification tools.
Leads hardware-software co-design for NXP’s edge microcontrollers in Catania, defining low-level drivers, ensuring silicon readiness, and enabling SDK integration for industrial and IoT applications.
Senior engineer integrates and optimizes high-speed switch silicon chips, collaborating with architecture, design, and firmware teams to meet timing, power, and area targets.
Leads digital IP design and architecture for NXP’s MCU/MPU portfolio, focusing on flash controllers, bus bridges, and ECC algorithms using Verilog/SystemVerilog and ARM cores.
NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a dynamic, technology-focused…
Designs and implements high-speed modem PHY IP for Blue Origin’s Terawave satellite network, translating algorithms into ASIC/FPGA hardware for next-gen space-based communications.
Designs and optimizes high-performance coherent interconnect IP and last-level cache blocks for Samsung's advanced semiconductor products, collaborating with architects, verification, and implementation teams.
Junior Member of Technical Staff - AI Silicon Digital Design Engineer About Unconventional Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental…
About Unconventional Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand…
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