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Verification Platform Engineer, Platform Architecture

Open 48d North America

Engineer in Apple's Platform Architecture group improving pre-silicon verification of Apple silicon by building testbenches, verification infrastructure, and simulation/emulation platform R&D to boost DV simulation throughput. Core tech: SystemVerilog (UVM, DPI-C), EDA tooling, C++ software development, and Python/Perl scripting.

Agentic AI AI C++ HPC Perl +4 skills

EDEKABANK AG | Hamburg

Mitarbeiter*in IT Helpdesk (m/w/d) (IT-Kundenbetreuer/in)

Open 35d Europe

Über uns Wir sind mehr als eine Bank: Als Partner im genossenschaftlichen Verbund begleiten wir das Wachstum der EDEKA-Kaufleute in ganz Deutschland. Mit Leidenschaft setzen wir uns dafür ein, dass über 400.000…

Director, ASIC Design Verification

Open 48d APACContract H-1B sponsor history

Directs SoC design verification strategy, methodology, and distributed teams at Ayar Labs in Bengaluru (on-site), hands-on with SystemVerilog/UVM verification of complex SoCs integrating ARM/RISC-V subsystems, coherent interconnects, memory, and high-speed I/O (PCIe, CXL, Ethernet, UCIe, SerDes) for AI, networking, and data-center applications.

Acceptance Criteria AI Analytics Automation CI/CD +14 skills

Principal Engineer, ASIC Design Verification

Open 48d APACPrincipal H-1B sponsor history

Ayar Labs is hiring a Principal Design Verification Engineer in Bengaluru to lead verification strategy for its next-generation silicon photonic (co-packaged optics) chip. The role involves architecting scalable UVM testbenches, setting verification methodology, debugging complex hardware issues, automating regressions, and mentoring engineers using SystemVerilog/UVM, protocol knowledge (PCIe, AMB

AI Asic Automation Bash C++ +9 skills

Sr. Engineer, ASIC Design Verification

Open 48d APACSenior H-1B sponsor history

Senior ASIC Design Verification Engineer at Ayar Labs (Bengaluru, on-site) doing pre-silicon verification of complex SoCs with digital and mixed-signal blocks: building SystemVerilog/UVM testbenches, test plans and coverage closure for SerDes, parallel-link and on-chip interconnect IP within a small startup IC design team.

AI Asic Python SerDes Uvm +1 skills

SG ASIC/SoC Design Verification Engineer

Responsibilities: Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification Build and maintain infrastructure/environment for automation…

AI Assembly Automation Bash C++ +7 skills

SG ASIC RTL/SoC Design Engineer

Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. Integrate and validate IP blocks within the larger system, ensuring…

AI Asic FPGA Image Processing Rtl +3 skills

ASIC/SoC Design Verification Engineer

Open 48d North America

Responsibilities: Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification Build and maintain infrastructure/environment for automation…

AI Assembly Automation Bash C++ +7 skills

ASIC RTL/SoC Design Engineer

Open 48d North America

Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs Integrate and validate IP blocks within the larger system, ensuring seamless…

AI Asic FPGA Image Processing Rtl +2 skills

Integrated Worlds

Dynamics 365 & Microsoft 365 Engineer (m/w/d)

Open 48d HybridEurope

Diese Stelle ist nur für Deutschland ausgeschrieben, weshalb Bewerber gesucht werden, die ihren Wohnsitz in Deutschland haben. Standort: Holzgerlingen. Sie kennen große IT-Umgebungen – jetzt wollen Sie gestalten statt…

Azure Business Intelligence Dataverse Entra ID GitHub +11 skills

SoC Design Verification Engineer, Google Cloud

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…

AI Cloud GCP Networking SystemVerilog +2 skills

Ingénieur FPGA – Secteur Aérospatial (H/F)

Open 48d Europe

Rejoignez une équipe d’experts en conception/validation FPGA pour des systèmes critiques chez des leaders mondiaux de l’aérospatial. Nous recherchons des ingénieurs spécialisés capable de développer et de valider des…

FPGA Python Uvm Verilog VHDL

FPGA Design Technical Leader- Ethernet, PCIe - 10+ Years

Meet the Team We are part of the Common Hardware Group, with our team specializing in FPGA development. Our work spans both sophisticated data-path and challenging control-path FPGAs. The design process includes…

AI Cisco Ethernet FPGA I2c +8 skills

FPGA Electrical Engineer II (Onsite)

Open 48d On-siteNorth AmericaFull-time

Date Posted: 2026-09-02 Country: United States of America Location: US-TX-MCKINNEY-513WD ~ 2501 W University Dr ~ WING D BLDG Position Role Type: Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements:…

Agile Asic Embedded Systems FPGA SystemVerilog +3 skills

FPGA Electrical Engineer I (Onsite)

Open 48d On-siteNorth AmericaFull-time

Date Posted: 2026-09-02 Country: United States of America Location: US-TX-MCKINNEY-513WD ~ 2501 W University Dr ~ WING D BLDG Position Role Type: Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements:…

Agile Asic Embedded Systems FPGA SystemVerilog +3 skills

Staff Design Verification Engineer

Open 47d APACStaff

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…

Machine Learning Uvm Verilog Virtualization

Senior CPU Design Verification Engineer

Open 47d APACSenior

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…

Machine Learning SystemVerilog Uvm Verilog

Sr. Staff Engineer - Design Verification

Open 47d APACStaff

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…

CAD FPGA Machine Learning Prototyping SystemVerilog +2 skills

АО "НИИЭТ"

Ведущий инженер-конструктор

Open 47d CISLead

Обязанности: Разработка планов верификации тестируемых модулей и устройств в целом; Реализация компонентов верификационного окружения по заданным требованиям; Реализация компонентов для измерения функционального…

Git SVN SystemVerilog Uvm Verilog +1 skills

Cardiac Sonographer

Building Name: PMC - CardiologyLocation Address: 115 Porter Drive, Middlebury VermontRegularDepartment: Porter - Medicine - Cardiology DivisionFull TimeStandard Hours: 40Biweekly Scheduled Hours:Shift: Day-8HrPrimary…