Sr. Engineer, ASIC Design Verification
Summary
Senior ASIC Design Verification Engineer at Ayar Labs (Bengaluru, on-site) doing pre-silicon verification of complex SoCs with digital and mixed-signal blocks: building SystemVerilog/UVM testbenches, test plans and coverage closure for SerDes, parallel-link and on-chip interconnect IP within a small startup IC design team.
Sr. Engineer - ASIC Design Verification
Location: Bangalor (on-site, flexible hours)
Location: Bangalor (on-site, flexible hours)
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
Backed by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
Summary:
This role is responsible for pre-Si verification and validation of complex SoCs with both high-speed custom and digital blocks. You will work in a dynamic startup environment as part of a small IC design team. The ideal candidate is a hands-on self-starter who can craft design specifications, verification suites and test-benches based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.
Essential Functions:
- Develop verification methodology and testbenches for digital and mixed-signal blocks
- Test plan, coverage analysis and closure for parallel link and SerDes IP blocks and on-chip interconnects
- Design and contribute to design for test (DFT) methodologies
Basic Qualifications:
- BS, MS in Electrical Engineering, Computer Engineering or equivalent
- 2+ years of ASIC verification experience
- 2+ years of System Verilog, UVM testbench development for design verification of complex digital and PHY blocks (in AMS and WREAL modeling verification)
- 2+ years of scripting and/or programming skills
Preferred Qualifications:
- Experience working on digital designs with multiple clock domains and clock dividers
- Post- place-and-route functional verification (NCSIM, VCS, ModelSim)
- Experience in verification of SerDes IP block interfaces in a complex SoC fabric environment
- Experience in verification of the PCS, PMA SerDes layers and internal SerDes digital backends
- Experience with verification of HBM memory interfaces (PHY and controller)
- Experience in formal model equivalence checking tools and verification methodology
- Programming experience in Python
Recruiters:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and please don't contact our managers or employees.
