Tech jobs — page 6 · freehire

/

Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.

Get the CLI →

1.8K jobs

Posted Sort

1,788 jobs Posted Sort

Integrated Circuit Design Verification Engineer

NewBe an early applicant RemoteNorth AmericaFull-time

IC design verification engineer on Snap's Spectacles team, verifying display integrated circuits for AR eyewear by building UVM/assertion-based testbenches, executing coverage-driven verification plans, and automating flows. Core stack: SystemVerilog/UVM, Siemens Questa, Verilog RTL, and TCL/Python/Perl/Shell scripting on Linux, working on-site 4+ days per week.

Asic Automation Bash Express.js I2c +8 skills

147K – 259K $

Digital Design Engineer (Mid-Senior Level)

NewBe an early applicant On-siteMENAFull-timeSenior

Movandi, a 5G mmWave technology company, is hiring a Digital Design Engineer in Riyadh to own complex digital subsystems: leading RTL design and verification for FPGA/ASIC targets, driving microarchitecture and timing closure, and doing lab bring-up and debug. Core tools include SystemVerilog/VHDL, cocotb, Vivado, Cadence Genus/Innovus/Xcelium, Python/Tcl, and Git.

Automation Bash C++ Embedded Software Ethernet +16 skills

SOC Design Verification Engineer

NewBe an early applicant North America

Verifies Apple's next-generation wireless SOC silicon: owns pre-silicon RTL verification from test planning through coverage closure and signoff, building reusable SystemVerilog/UVM testbenches across blocks like the CPU subsystem, PCIe, DMA, and MAC-PHY, including low-power/UPF verification and exploring AI-assisted verification workflows.

AI Assembly C++ Firmware Machine Learning +8 skills

Senior FPGA Verification Engineer

Open 52d HybridUKContractSenior H-1B sponsor history

Senior FPGA Verification Engineer develops and maintains advanced UVM/SystemVerilog test benches for quantum control systems, ensuring reliability and performance through constrained-random testing, coverage analysis, and CI pipelines.

Automation CI/CD Cloud Cybersecurity Financial Modeling +8 skills

Wireless PHY Systems Engineer — Pre-Silicon Emulation

New North America

Owns the pre-silicon emulation environment (Palladium) for Apple's wireless SoC team: bringing up each emulated Bluetooth/UWB build and building bring-up infrastructure (register maps, boot sequences, clock/reset, system config) so the team can verify new silicon designs before tape-out. Core stack: MATLAB, C/C++, DSP, wireless PHY/MAC.

Automation CI/CD C++ Firmware FPGA +8 skills

Senior Silicon Logical Design Engineer - Bengaluru

Open 47d APACSenior

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed…

AI Automation Python Rtl SystemVerilog +1 skills

Director, Silicon Logical Design

Open 127d UK Licensed UK sponsor

Leads a global team designing the microarchitecture and RTL for Graphcore’s AI accelerators, ensuring performance, power, and schedule targets while collaborating with architecture, physical design, and verification groups.

AI Automation Program Management Python Rtl +3 skills

Staff Silicon Logical Design Engineer - Bengaluru, Multiple Vacancies

Open 93d APACStaff Licensed UK sponsor

Designs and integrates advanced semiconductor logic for AI chips in Bengaluru, using SystemVerilog, Python, and digital design flows to deliver RTL and microarchitecture for Graphcore’s silicon.

AI Automation Python Rtl SystemVerilog +1 skills

SOC and IP Design Engineer, Google Cloud

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…

AI Cloud FPGA GCP Machine Learning +4 skills

500 Intel Ireland Ltd.

USB IP Design Verification Engineer

New HybridAPACFull-time

Entry-level (0-1 yrs) design verification engineer at Intel working on USB IP development for client products: defining validation test plans, building testbench infrastructure (monitors, scoreboards, BFMs), and closing coverage using SystemVerilog, with Verilog/VHDL RTL basics; UVM/OVM and USB protocol knowledge preferred. Hybrid role based in Penang/Kulim, Malaysia.

AI ChatGPT GitHub Github Copilot Rtl +3 skills

Senior Silicon Engineer, HBM Memory Subsystem Design, Integration and Validation

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML…

AI Cloud GCP Machine Learning Networking +4 skills

Advanced Micro Devices, Inc

DFT Architect

Senior silicon design engineer on AMD's Server CPU team in Bangalore, implementing structural Design-for-Test (DFT), ATPG, and LBIST for next-generation EPYC server SoCs — defining test architecture with RTL and physical design teams, generating and validating manufacturing test patterns, and supporting silicon bring-up, using tools like Siemens Tessent and scripting in Perl/Python/Tcl.

AI Automation Bash Cloud Go-to-Market +6 skills

Senior Recruiter, Hardware

New RemoteNorth AmericaSenior

Positron AI builds purpose-built hardware and software for efficient AI inference and is hiring a Senior Hardware Recruiter to own full-cycle hiring for its silicon and systems teams — sourcing and closing semiconductor engineers (ASIC/RTL, verification, physical design, DFT, validation), partnering with engineering leaders, and using an agent-first, AI-driven recruiting approach.

Agentic AI AI Automation Candidate Experience Firmware +3 skills

140K – 225K $

Senior ASIC Physical Design Engineer

Open 79d RemoteWorldwideSenior

Lead end-to-end ASIC physical design from RTL to GDSII tapeout, optimizing power, performance, and area using Cadence/Synopsys flows for high-security microelectronics.

Senior ASIC Design Engineer

Open 74d HybridAPACSenior

Designs and automates ASIC synthesis flows for coherent optics chips, using scripting (Python/Perl/TCL) and Synopsys EDA tools to improve timing, power, and reliability across global teams.

AI API Asic Ethernet FPGA +3 skills

USB IP Design Verification Engineer

New HybridAPACFull-time

Job Details: Job Description: Passionate IP design Verification Engineer who is motivated to work on fast moving USB IP development across various Client products. The engineer will have an opportunity to define a…

AI ChatGPT GitHub Github Copilot Rtl +3 skills

ASIC Digital Design, Sr Staff Engineer- 19060

Job Description and Requirements We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning…

AI Automation Perl Python Rtl +1 skills

ASIC Digital Design, Sr Staff Engineer - 19281

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…

AI Asic Ethernet PCIe Pre-sales +3 skills

Principal FPGA/ASIC Engineer (Onsite)

New On-siteNorth AmericaFull-timePrincipal

Date Posted: 2026-10-15&#xa;&#xa; Country: United States of America&#xa;&#xa; Location: US-CA-EL SEGUNDO-E04 ~ 2006 E El Segundo Blvd ~ BLDG E04&#xa;&#xa; Position Role Type:…

C++ FPGA Git Perl Rtl +6 skills

Senior Principal FPGA/ASIC Engineer (Onsite)

New On-siteNorth AmericaFull-timePrincipal

Date Posted: 2026-10-15&#xa;&#xa; Country: United States of America&#xa;&#xa; Location: US-CA-EL SEGUNDO-E04 ~ 2006 E El Segundo Blvd ~ BLDG E04&#xa;&#xa; Position Role Type:…

C++ FPGA Git Perl Rtl +6 skills