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Lead embedded firmware development for Marvell’s DSP-based optical networking chips, guiding a small team to deliver firmware that controls signal processing, FEC, and thermal monitoring for data-center interconnects.
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Designs high-speed NAND datapath and DDR interfaces for memory chips, optimizing CMOS circuits for performance, power, and signal integrity using SPICE and RTL/Verilog flows.
Design and implement timing-critical RTL blocks for memory/storage chips using SystemVerilog, focusing on latency, CDC, reset logic, and PVT-aware coding for advanced process nodes.
Designs and validates security IP blocks (e.g., cryptographic accelerators, root-of-trust) for Microsoft’s cloud hardware, collaborating with SoC and firmware teams to deliver secure, high-performance RTL solutions.
Lead AMD’s pre-silicon verification strategy, defining next-gen architectures and methodologies to ensure first-pass silicon success for complex SoC designs using advanced EDA tools and ML/AI innovations.
Designs and verifies peripheral IP blocks (PCIe, CXL, USB, Ethernet) using SystemVerilog/UVM, coverage-driven random testing, and C-based reference models.
Develops embedded software for FPGA and microcontrollers, integrates with hardware, and writes HDL (VHDL/Verilog) to build avionics and embedded systems.
Design verification engineer building UVM testbenches for high-speed interconnects (PCIe, CXL, AXI) to ensure ASIC/subsystem correctness before tape-out.
Designs and verifies hardware infrastructure, focusing on DDR subsystem verification for Qualcomm’s next-gen products. Uses UVM, SystemVerilog, and debug tools to create test plans, integrate verification IP, and ensure high-quality verification of digital/analog/RF systems.
Video Codec Design Engineer, up to Staff Location: Taipei, Taipei City, Taiwan Department: ASICS Engineering Work Location: onsite Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group…
Designs and optimizes CPU physical layouts using Place & Route tools (FC/Innovus), STA (Primetime/Tempus), and UPF/CPF for low-power, high-speed ASICs.
Senior C/C++ engineer building Electronic Design Automation tools that help global manufacturers design chips and systems faster and more cost-effectively.
Develop and maintain emulation models and infrastructure for Google’s custom silicon, scripting automation and debugging hardware flows to accelerate product development.
Design verification engineer building and debugging SystemVerilog/UVM testbenches for custom AI silicon IP and SoCs, ensuring functionally correct RTL before tape-out.
Lead a hardware engineering team to design and scale production of quantum computing orchestration systems, focusing on testability, failure analysis, and production readiness.
Designs and implements RTL logic for Intel’s IP blocks, focusing on secure memory access, error handling, and debug/telemetry features to ensure high-performance SoC reliability.
Develops a new automation tool for silicon CAD (chassis automation) to generate RTL, register definitions, and verification collateral from user requirements, collaborating with RTL, verification, and SoC teams using Python, structured schemas, and CI/CD pipelines.
Design and verify RTL hardware designs and SystemVerilog/UVM testbenches to train AI agents that automate chip design workflows.
Applications Engineer at ChipAgents guides enterprise customers through AI-driven chip design and verification workflows, integrating tools like Synopsys VCS and Cadence Xcelium to accelerate RTL development and verification.
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