Backend Engineer – Synthesis
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Summary
Backend engineer doing RTL-to-gate-level logic synthesis and Design-for-Test (scan insertion, ATPG, MBIST, boundary scan) for digital SoC modules, collaborating with RTL and place-and-route teams on SDC, timing, and PPA closure. Core tools: EDA flows like DC/FC/TetraMax, with Verilog, TCL, Perl, and Python scripting.
Job Responsibilities
- Responsible for synthesis from RTL to gate-level netlist
- Work with RTL design team to create and verify SDC
- Work with PnR engineers to improve PPA of digital modules
- Responsible for the DFT (Design for Test) tasks of the entire chip or module, including synthesis, scan insertion, ATPG, MBIST, boundary scan, and functional testing.
- Collaborate with front-end and back-end teams to perform DFT-related STA, power, and IR drop analysis, ensuring timing closure for DFT designs.
Qualifications
- Bachelor’s degree or higher in Microelectronics, Electronic Engineering, or a related field.
- Familiarity with backend design flow and tools; experience with EDA tools such as DC/FC/TetraMax is preferred.
- Experience in physical implementation and physical verification for large-scale chips at 28nm or below.
- Proficiency in Verilog, TCL, Perl, and Python is a plus.
- Strong communication, stress management, and teamwork skills, with the ability to work effectively in a cross-departmental environment.