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Micron Technology
4 views 2 months ago

SR ENGINEER, DDEG Design Methodology

Open 52d APACSenior
India

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…

Agentic AI AI Automation Cmos Perl +4 skills
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Micron Technology
10 views 2 months ago

STAFF ENGINEER, DDEG Design Methodology

Open 52d APACStaff
India

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…

Agentic AI AI Automation Cmos Perl +4 skills
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onsemi
8 views 2 months ago

Senior Design Verification Engineer

Open 52d EuropeSenior
Czechia

Join onsemi’s new and growing RISC-V division and help ensure the functional correctness, quality, safety, and security of configurable and customizable RISC-V CPU IP. You will participate in the complete verification…

AI Iso 26262 Rtl SystemVerilog Uvm
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Cadence
7 views 2 months ago

Senior Software Engineer - Low Power Verification

Open 52d APACSenior
Taiwan

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our team and help build the next generation of low-power verification software for the Palladium and…

AI C++ Perl Prototyping Python +5 skills
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Booz Allen
12 views 2 months ago

University - Summer 2027 Electronic Warfare FPGA Engineering Intern

Open 52d North AmericaInternshipIntern
United States

University - Summer 2027 Electronic Warfare FPGA Engineering Intern The Opportunity: Join a team developing advanced capabilities in electronic warfare and software defined radio systems. As an FPGA Engineering Intern,…

AI Embedded Systems FPGA Signal Processing SystemVerilog +2 skills
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A2e Technologies
7 views 2 months ago

Sr. FPGA Design Engineer

Open 47d North AmericaContractSenior
United States

Title: Sr. FPGA Design Engineer Location: Redmond Term: Contract (possible Perm) Duration: Long-Term Contractor/Perm Start Date: ASAP Requirements 10+ Years experience: FPGA/Modem Design Ultrascale+ & Versal VHDL &…

Bash Ethernet FPGA I2c PCIe +6 skills
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BTA Design Services
4 views 2 months ago

Senior FPGA Design Engineer

Open 41d On-siteNorth AmericaContractSenior Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada

About BTA Design Services Headquartered in Ottawa, BTA Design Services supports the electronic design community across Canada and internationally, specializing in ASIC and FPGA design, verification, and embedded…

CAD Embedded Software FPGA Networking Python +3 skills
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hctz.fa.us2.oraclecloud.com/CX
3 views 2 months ago

Senior Design Verification Engineer

EuropeSenior
Czechia

Join onsemi’s new and growing RISC-V division and help ensure the functional correctness, quality, safety, and security of configurable and customizable RISC-V CPU IP. You will participate in the complete verification…

AI Iso 26262 Rtl SystemVerilog Uvm
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L3Harris Technologies
2 months ago

Manager; Electrical Engineering (FPGA) 1

North America
United States

L3Harris is dedicated to recruiting and developing high-performing talent who are passionate about what they do. Our employees are unified in a shared dedication to our customers’ mission and quest for professional…

Asic Firmware FPGA Signal Processing SystemVerilog +3 skills
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Apple Backed by Sequoia
8 views 2 months ago

Verification Platform Engineer, Platform Architecture

Open 53d North America
United States

Engineer in Apple's Platform Architecture group improving pre-silicon verification of Apple silicon by building testbenches, verification infrastructure, and simulation/emulation platform R&D to boost DV simulation throughput. Core tech: SystemVerilog (UVM, DPI-C), EDA tooling, C++ software development, and Python/Perl scripting.

Agentic AI AI C++ HPC Perl +4 skills
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Ayar Labs
12 views 2 months ago

Sr. Staff Engineer, ASIC Design

Open 54d APACStaff H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

A senior ASIC design engineer who designs, verifies, brings up, and debugs digital subsystems in electro-optical SoCs for Ayar Labs' co-packaged optics that move data for AI systems. Day to day: RTL in Verilog/SystemVerilog, testbenches, timing constraints and documentation, and Python-driven silicon bring-up.

AI Asic Cadence Virtuoso C++ Firmware +5 skills
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Ayar Labs
12 views 2 months ago

Sr. Staff Engineer, Front-End CAD / Design Automation

Open 54d APACStaff H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Owns and scales the front-end CAD/design automation flows for Ayar Labs' ASIC and SoC teams in Bengaluru: building Python/Tcl/Shell/Make tooling for lint, CDC/RDC, regressions, and signoff readiness, supporting Synopsys/Cadence/Siemens EDA deployments, and championing AI-assisted CAD agents and workflows.

AI Asic Assembly Automation Bash +14 skills
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Ayar Labs
9 views 2 months ago

Sr. Staff Engineer, ASIC Design

Open 54d North AmericaStaff H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Sr. Staff Engineer designing and debugging digital subsystems for Ayar Labs' electro-optical ASICs (co-packaged optics that move AI data over light). Day to day: writing RTL in Verilog/SystemVerilog, building testbenches, defining timing constraints, and doing silicon bring-up/debug with Python, C/C++, and firmware — on-site in San Jose.

AI Asic Cadence Virtuoso C++ Firmware +5 skills
180K – 223K $
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Ayar Labs
15 views 2 months ago

Director, ASIC Design Verification

Open 54d APACContract H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Directs SoC design verification strategy, methodology, and distributed teams at Ayar Labs in Bengaluru (on-site), hands-on with SystemVerilog/UVM verification of complex SoCs integrating ARM/RISC-V subsystems, coherent interconnects, memory, and high-speed I/O (PCIe, CXL, Ethernet, UCIe, SerDes) for AI, networking, and data-center applications.

Acceptance Criteria AI Analytics Automation CI/CD +14 skills
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Ayar Labs
6 views 2 months ago

Principal Engineer, ASIC Design Verification

Open 54d APACPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Ayar Labs is hiring a Principal Design Verification Engineer in Bengaluru to lead verification strategy for its next-generation silicon photonic (co-packaged optics) chip. The role involves architecting scalable UVM testbenches, setting verification methodology, debugging complex hardware issues, automating regressions, and mentoring engineers using SystemVerilog/UVM, protocol knowledge (PCIe, AMB

AI Asic Automation Bash C++ +9 skills
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TetraMem
8 views 2 months ago

SG ASIC RTL/SoC Design Engineer

Open 54d APAC H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Singapore

Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. Integrate and validate IP blocks within the larger system, ensuring…

AI Asic FPGA GPU Image Processing +4 skills
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TetraMem
9 views 2 months ago

SG Hardware - Digital Intern

Open 54d APACInternshipIntern H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Singapore

About the Role We are seeking a Digital Hardware Intern to support the design, verification, and integration of digital systems in TetraMem’s AI accelerators. You’ll contribute to RTL design, simulations, and…

AI Asic Bash Python Rtl +3 skills
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TetraMem
10 views 2 months ago

US 2026 Hardware - Digital Intern

Open 54d North AmericaInternshipIntern H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

About the Role We are seeking a Digital Hardware Intern to support the design, verification, and integration of digital systems in TetraMem’s AI accelerators. You’ll contribute to RTL design, simulations, and…

AI Asic Bash Python Rtl +3 skills
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IC Enable
10 views 2 months ago

Analog Design Engineer - Neuromodulation

Open 54d North America H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Own and lead the development of analog integrated circuits for neuromodulation medical devices—from first principles through silicon and into real-world use. You’ll work on ultra-low-power designs that interface…

MATLAB Python SystemVerilog
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IC Enable
12 views 2 months ago

RTL Design Engineer

Open 54d North AmericaFull-time H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

IC Enable is seeking an experienced RTL Design Engineer to support digital IC development from architecture through implementation. This role is ideal for an engineer with strong Verilog/SystemVerilog RTL design…

Firmware Itar Rtl SystemVerilog Verilog
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