Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Lead Software Engineer specializing in Verification IP (VIP) development for electronic design software, focusing on layered protocols like UCIe, PCIe, CXL, and Ethernet using SV/UVM, with hands-on C/C++ scripting and cross-functional collaboration.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Designs and verifies hardware components for Microsoft's cloud infrastructure, focusing on formal verification methods and AI-driven solutions to ensure chip reliability and performance.
About The Role We are looking for a System Hardware Engineer with strong system hardware development and troubleshooting capabilities. This role will participate in the full product development lifecycle, from…
Design next-generation Adaptive SoCs, focusing on compute, memory, AI, I/O, power, and advanced packaging to deliver high-performance, power-efficient solutions for AI, data center, and embedded systems.
QA engineer builds and runs test labs for server hardware, storage, and low-level firmware (BIOS/BMC), automates tests with Bash/Python, and documents defects while validating Linux, virtualization, and storage-area networks.
Leads cross-functional programs to design, validate, and deploy next-generation AI networking infrastructure, including high-speed optical interconnects and hyperscale datacenter systems.
Define the end-to-end hardware, software, and management architecture for next-generation AI scale-up network chassis, including UALink switch fabrics, power/cooling orchestration, and BMC/OpenBMC-based platform management.
Define and build low-level firmware for next-gen AI cluster switches, bridging silicon and orchestration software to maximize bandwidth, minimize latency, and ensure reliability across thousands of AI accelerators.
Location: This role is based onsite at our office in Louisville, CO, with the option to work a few days a week remotely. Travel: Up to 5% Job ID: 568 About Capella Capella, an IonQ company, spans national security,…
Designs and delivers flight-ready PCBs for space systems, shepherding analog/digital boards from concept through orbit while collaborating with RF, mechanical, and software teams.
Develop and verify low-level Linux drivers and test plans for x86 CPU features, collaborating with hardware and firmware teams to debug and improve system performance.
Lead a team to architect and deliver embedded HPC software stacks (Linux/QNX/Android) for automotive platforms, focusing on real-time and application cores while mentoring engineers and ensuring Q-C-D targets.
Design and implement verification environments for AMD’s Network-on-Chip IPs and SoCs using SystemVerilog/UVM, formal tools, and coverage-driven flows to ensure functional correctness.
About the role: We’re looking for an experienced GPU Driver Developer. You will focus the design, development, implementation, and toolchain of a high-performance host-side driver stack and API for our proprietary…
Define and implement firmware for next-gen AI cluster switches, bridging ASIC silicon with cluster orchestration software to maximize bandwidth, minimize latency, and ensure reliability across thousands of AI accelerators.
Lead the architecture and RTL design of high-speed switching fabrics for next-gen memory and AI interconnects, guiding teams from spec to silicon bring-up.
Principal Engineer leads verification strategy for next-gen UA Link Switch SoCs, using UVM/SystemVerilog to ensure first-silicon success for high-speed interconnect and memory subsystems.
Principal Design Engineer at Rambus to architect and implement next-gen PCIe IP in System Verilog, prototype on FPGAs, and collaborate with global teams.
Drive pre-sales technical engagement for Ciena’s high-speed optical interconnect solutions, validating performance and guiding AI/cloud partners through design wins and deployments.
We couldn't check your fit for this role — add a CV to your profile to see it next time.
