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Principal Physical Design Methodology Engineer - 18396
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Serdes IP Design Engineer---18478
Seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. The candidate would be working as part of a highly experienced mixed-signal design and verification team,…
DFT Architect
About the role We are looking for an experienced DFT Architect to lead Design-for-Test strategy, architecture definition, and implementation for complex ASIC/SOC designs across advanced technology nodes. The ideal…

Silicon Validation/Emulation Design Engineer
As a Silicon Validation/Emulation Design Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators, as well as multiple ARM-based sub-systems. You will be a key contributor in our…
Senior Design Engineer (CAD & Methodology)
About Bitdeer Technologies Group Bitdeer is a world-leading technology company for AI and Bitcoin mining infrastructure. Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers and…
Silicon Product & Test Engineer
Drive post-silicon productization of bitcoin mining ASICs from bring-up through mass production, developing ATE test programs, optimizing yield, and performing silicon data analysis across cross-functional teams.


ASIC Physical Design Intern - 2027
An ASIC physical design intern at NVIDIA works on chip implementation tasks from RTL freeze to tapeout, focusing on synthesis, verification, constraints, timing closure, and methodology development for high-frequency, low-power designs.


ASIC Physical Design Engineer (RDSS Intern)
An intern ASIC Physical Design Engineer at NVIDIA works on chip implementation from RTL freeze to tape-out, handling synthesis, verification, constraints, timing closure, and methodology development for high-performance, low-power digital chips.
Staff Physical Design Engineer, HBM
Designs and implements high-performance, low-power memory logic from netlist to GDSII, focusing on timing closure, power integrity, and manufacturability in advanced process nodes.
Design Engineer - STA
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