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Hands-on DevOps/Infrastructure Engineer in Dubai who operates, secures, and improves mostly on-premises infrastructure for a networking OS and AI-chip company. Day to day spans Linux administration, identity/access management, virtualization, storage, Docker, networking, security, and air-gapped environment operations.
As a member of the DFP (Design For Power) team you will be responsible for developing and defining low power implementation and EMIR signoff methodology of world class chips under most advanced tech node. Your…
JOB DESCRIPTION · Work with system engineers on timing requirements and feedback on optimization. · Work on SoC timing constraint, synthesis and timing closure. · Work on power structure, eg. Isolation of power…
JOB DESCRIPTION · Discussion with system engineers on IP requirement and micro architecture. · Develop IP (control path intensive or data path intensive) meet functional requirement and protocol standard. · Support SoC…
JOB DESCRIPTION In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition • Develop detailed module level and SoC level testplans for all the…
Change people’s lives and love what you do! Cochlear develops world-leading medical devices that help people hear. As a top 100 medical device company and market-leader in implantable hearing devices, more people…
Annapurna Labs is the team behind AWS (Amazon Web Services) Graviton — the industry's most advanced Arm-based server CPU — and we operate like a start-up with the scale of the world's largest cloud provider.…
Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and…
Job Title: Sr. ASIC & FPGA Design Engineer Position Type: Contracted - 10/12/2026 - 06/30/2027 Job Type: 100% Remote (If Converted to full time, you will have to relocate to one of the client location, Southern…
We are now looking for a ASIC Verification Engineer. NVIDIA SOC System-ASIC team is hiring a senior verification engineer. In this role, you will work closely with Arch, design and verification engineers to thoroughly…
NVIDIA System-On-Chip (SOC) group is hiring for an ASIC Design Engineer! The complexity of the chips we build has increased manifold over the years. We are now packing tens of billions of transistors in a chip to meet…
Amazon LEO is an initiative to increase global broadband access through a constellation of 3,236 satellites in low Earth orbit (LEO). Its mission is to bring fast, affordable broadband to unserved and underserved…
VLSI Design Verification InternThis role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global…
L3Harris is dedicated to recruiting and developing high-performing talent who are passionate about what they do. Our employees are unified in a shared dedication to our customers’ mission and quest for professional…
At AMD's Markham, Ontario site, this engineer builds full-stack apps, APIs, dashboards, and automation plus AI-powered developer tools that boost engineering productivity across ASIC design and verification teams, using React/Angular/Vue, PostgreSQL/MySQL/MongoDB, Linux, Python, CI/CD/DevOps, and AI-assisted coding tools like Claude Code and Codex.
Designs next-generation ASICs and FPGAs for SpaceX's Starlink satellites and ground infrastructure: RTL design and SoC integration in SystemVerilog/Verilog, power-performance-area optimization, participation in the full design lifecycle, and lab bring-up/validation, collaborating with systems, firmware, architecture, and backend teams.
What are your contributions to the team? In your role, you will review and assess supplier’s airborne software and electronic hardware designs to ensure they meet Bombardier’s technical requirements and regulatory…
Overview of Role As an IP Alliance Manager you will work with vendors from the TSMC’s IP Alliance. Responsibilities include enabling IP vendors to populate the IP Ecosystem on TSMC’s technology. You will directly work…
Supports semiconductor Foundation IP development at Capgemini Engineering in Brasov, Romania: implementing and validating RTL Verilog design changes, running QA checks, and managing ClearCase-based IP release flows with Python automation. Core tech: Verilog/SystemVerilog, ASIC design, CDC/Lint, AMBA protocols, Linux.
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