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Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. The Role:…
Designs and leads ASIC SoC architecture for Amazon’s Ring/Blink smart home devices, focusing on low-power AI/video processing and CMOS tech to enhance customer safety and connectivity.
Manage complex hardware R&D programs at Nokia in Canada, coordinating from prototypes through NPI across engineering, operations, procurement, and external ASIC/IC suppliers.
Lead embedded software architecture and hardware/software co-design for semiconductor platforms at Analog Devices in Limerick, working with C/C++, RTOS, FPGA/SoC, and JTAG debugging tools.
Lead RTL-to-GDSII physical design implementation for next-gen high-performance processor/ASIC chips, managing teams, methodology, and tapeouts using advanced EDA tools and scripting (Tcl, Python, Perl).
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software…
Lead RTL/silicon design engineer for AMD's Data Accelerator team, designing custom hardware offload engines (encryption, compression, compute offloads) for SOCs powering servers, datacenters, and embedded products.
Senior Analog/Mixed-Signal IC Designer at Bosch responsible for the full development flow of high-performance analog and mixed-signal circuits for automotive ASICs in electrification and smart power, using Cadence Virtuoso and Verilog-A/AMS.
Designs and implements ASIC IPs and system features for Mobileye’s next-gen SoC, focusing on ADAS and autonomous vehicle technologies, including RTL development, verification, synthesis, and timing closure.
Develops ASIC physical designs for Cisco’s hardware platforms, focusing on fullchip floorplanning, RTL-to-GDSII implementation, and optimization of performance/power/die size using advanced EDA tools and methodologies.
Leads research in open-source processor/accelerator architectures (RISC-V, AI) using Verilog/SystemVerilog and EDA tools, publishing findings and mentoring junior researchers.
This role involves developing FPGA-based control and protection systems for high-voltage direct current (HVDC) power transmission technology. The engineer will participate in the full design cycle, including simulation, prototyping, and testing using VHDL and related tools within an international R&D team.
Design and evaluate analog, digital, mixed-signal, power, and RF circuits to train AI models in electrical engineering, ensuring technical correctness and real-world applicability.
Join Solidigm’s visionary Design Engineering Team as a 3D NAND IP Logic Design Engineer and help shape the future of memory technology. Job responsibilities include, but not limited to: Architect, design, and verify…
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify…
This role involves evaluating third-party analog and mixed-signal IP designs to ensure they meet AMD specifications and manufacturing standards. The engineer will use EDA tools and develop automation scripts to analyze circuit performance and resolve design issues before silicon manufacturing.
This role involves evaluating third-party analog and mixed-signal IP designs for AMD processors, ensuring they meet specifications through pre-silicon verification and CAD automation. The engineer will develop scripts and leverage AI tools to improve design analysis workflows and resolve hardware issues before manufacturing.
Design and verify custom ASICs for ultra-low-latency trading systems using SystemVerilog, C++, and Python, collaborating with hardware, software, and trading teams.
Leads a team designing high-performance, low-power System-on-Chip (SOC) components using Verilog/System Verilog, UPF, and industry-standard EDA tools.
RTL/SOC integration design engineer at AMD Hyderabad, responsible for ASIC design in sub-20nm nodes using Verilog/SystemVerilog, timing analysis, low-power design, and SOC verification tools.
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