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Principal Product Engineer at Cadence to drive backend design flows in Virtuoso for advanced process nodes, combining IC layout, automation, and customer engagement.
Mixed Signal IC Layout Design Engineer - Contractor Location: North America Department: Mixed Signal Design Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations,…
NXP’s Austin Memories team is seeking an experienced memory circuit design engineer for our SRAM and ROM internal memory compiler designs. Our team is part of the Design Enablement/Foundation IP organization within the…
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Sr. Principal Design Engineer Location: NOIDA 01 Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 1. Role Overview &…
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Senior Analog Layout Design Engineer Location: Bengaluru, Karnataka, India Department: Weekday's Client via platform Workplace: on_site Employment Type: full Description This role is for one of the Weekday's…
Designs memory circuits for AI hardware, focusing on performance, power efficiency, and scalability.
Sr Staff Mask Design Engineer Location: Bengaluru, KA, in Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world,…
Design physical layouts for SRAM and custom memory blocks using Cadence Virtuoso, verify with DRC/LVS, and collaborate with global teams to meet performance and manufacturability targets.
Designs and models analog/mixed-signal CMOS circuits for imaging sensors, using Cadence Virtuoso and SPICE tools, and collaborates with cross-functional teams.
Design and verify electrostatic discharge (ESD) protection circuits for advanced ASIC and FPGA chips using SPICE, PDKs, and EDA tools like Cadence Virtuoso.
Designs and verifies custom IC layouts for analog and digital circuits using Cadence Virtuoso and Mentor Calibre, including PLLs, DACs, and high-speed signaling blocks.
Designs and lays out CMOS and metallization test structures for semiconductor R&D, using EDA tools like Cadence Virtuoso and Calibre to enable DRAM/NAND process development and reliability analysis.
Senior SRAM Circuit Design Engineer Location: US, CA, Santa Clara, US, CA, Remote Time Type: Full time Job Description NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than…
We are looking for an experienced Sr Staff Mask Design Engineer to join a highly skilled layout organization working on Analog and Mixed‑Signal ICs for Automotive applications . The role involves defining, developing,…
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 1. Role Overview & Objective We are looking for a motivated SRAM Circuit Design Engineer to join our…
Summary Qorvo is seeking an experienced EDA Applications Engineer to define, deploy, and support silicon design methodologies across RF, analog, mixed-signal (AMS), and digital IC development. The role serves as the…
Designs and verifies analog and digital IC layouts (PLL, DAC, VCO, etc.) using Cadence Virtuoso and Mentor Calibre, from cell-level blocks to full chip integration.
Designs and verifies electrostatic-discharge protection circuits for advanced ASIC/FPGA chips using SPICE simulations, layout reviews, and foundry PDKs.
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