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Power Architect driving end-to-end power, performance, and area (PPA) excellence for EnCharge AI's next-gen AI inference chips: shaping SoC power/thermal architecture, guiding low-power RTL and floorplanning, building physical-design recipes, and customizing EDA power-analysis tools (PowerArtist, PrimePower, Joules) with Python/Tcl/Perl scripting.
FPGA Design Engineer owning the design and implementation of FPGA-based interfaces (PCIe, I2C, SPI, high-speed GT) on Xilinx UltraScale+ and Versal platforms for quantum computing control systems.
Hardware Design Verification Engineer at FuriosaAI responsible for defining and implementing verification plans, building test benches, and debugging design failures using SystemVerilog/UVM methodologies and EDA tools.
Designs and optimizes AI hardware architectures, focusing on performance, power, and area (PPA) metrics. Uses Verilog, EDA tools, and scripting to perform synthesis, equivalence checking, and timing analysis for chip-level designs.
Validates NPU SoC hardware for FuriosaAI, ensuring first-silicon bring-up, system-level debugging, and performance optimization across AI compute components like NPU cores, CPUs, and high-speed interfaces.
FuriosaAI is seeking a Software Engineer to design and implement high-performance kernels for their proprietary AI-native compute platform. The role involves optimizing AI model performance on hardware, developing diagnostic tools, and enabling end-to-end programming for AI workloads.
Leads silicon validation for NPU SoC chips, ensuring system-level functionality from first silicon bring-up to performance optimization and stability. Bridges hardware (RTL/DV) and software (firmware/OS) teams with structured validation processes, debugging, and test automation.
Software engineer on FuriosaAI's MLSys team enabling frontier LLMs on the company's NPU chips: analyzing model architectures, writing and optimizing Tensor Contraction Language (TCL) kernels (attention, MoE), integrating models into the Furiosa-LLM inference stack, and validating correctness and performance. Core stack: Python, PyTorch, TCL DSL, with Rust/C++ code reading and vLLM/SGLang technique
Software engineer on FuriosaAI's compiler team in Seoul who owns the performance of critical AI kernels in Furiosa-LLM: analyzing LLM serving workloads, finding bottlenecks, and writing highly optimized kernels in TCL (Tensor Contraction Language), plus developing scheduling and specialization techniques for dynamic serving workloads.
Senior/Principal Physical Design Engineer at Fractile, responsible for end-to-end ASIC/SoC physical design implementation (floorplanning, placement, CTS, routing, sign-off) using EDA tools like Cadence Innovus, Synopsys Fusion Compiler, and Mentor Graphics Calibre, optimizing PPA metrics and collaborating with cross-functional teams.
Ports ASIC RTL designs onto FPGA prototypes for pre-silicon emulation: refactoring clock/memory/analog blocks, running synthesis, place-and-route and timing closure in Xilinx Vivado, Intel Quartus or Synopsys ProtoCompiler, performing SpyGlass CDC sign-off, and bringing up boards with JTAG/logic analyzers while integrating PCIe, AXI, Ethernet and DDR interfaces.
Senior silicon design engineer at AMD in Bangalore focused on electromigration and IR-drop (EMIR) analysis, debug, and signoff closure for complex high-performance SoC designs using Ansys RedHawk-SC and Cadence Voltus. Works with physical design, power, and package teams to root-cause power integrity issues and improve EMIR methodology and automation.
Toporder est une plateforme qui accompagne les commerçants dans leur digitalisation: gestion des commandes, expérience client et pilotage de leur activité, de manière simple et efficace. Fin 2024, on a rejoint myPOS,…
We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation. Our current work is focused…
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and scripting.
At IBM, work is more than a job - it's a calling: To build. To design. To code. To consult. To think along with clients and sell. To make markets. To invent. To collaborate. Not just to do something better, but to…
Verifies and validates memory circuits, memory IP, and full-chip designs at a semiconductor company in Hyderabad: runs SPICE/FastSPICE and gate-level simulations, analyzes SRAM/DRAM timing across PVT corners, and builds testbenches and regression automation using Verilog/SystemVerilog and scripting like Python or Tcl.
Vantive is a vital organ therapy company on a mission to extend lives and expand possibilities for patients and care teams everywhere. For 70 years, our team has driven meaningful innovations in kidney care. As we…
Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment,…
