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FPGA Silicon Design Verification Engineer
Design Verification Engineer builds UVM testbenches and runs pre-silicon verification for FPGA DFT logic like scan, MBIST, and JTAG to ensure silicon quality before tape-out.
Senior FPGA Design Engineer
Design and verify FPGA-based systems using VHDL/SystemVerilog for aerospace/defense applications, collaborating with hardware and systems teams to meet DoD requirements.
Director, ASIC Design & Front-End Implementation
Lead a team designing and implementing high-performance networking ASICs from architecture to tapeout, collaborating with cross-functional teams to deliver silicon for HPE's networking products.
ASIC Digital Design, Staff Engineer - 18335
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Senior Design Engineer
As a Senior Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and…
ASIC Design and Integration Engineer
Designs and integrates custom ASICs for Apple’s SoCs using SystemVerilog, RTL, and synthesis while collaborating with hardware and software teams.
验证工程师
1. 负责复杂数字模块或子系统的 验证方案制定、环境搭建与覆盖率提升，确保设计功能符合规格要求。 2. 基于 UVM/SV 构建验证平台，包括激励生成、参考模型、Scoreboard、Checker 等关键组件。 3. 主导模块级与子系统级的 Testplan 设计、随机和定向用例开发，推动覆盖率闭环。 4. 负责定位与分析仿真问题，跨团队协作（前端设计/架构/PD/DFT）推动问题根因定位与修复。 5. 支持 Gate-level…
数字设计工程师
1. 负责数字芯片核心模块的 RTL 设计、优化与交付，确保功能、时序及低功耗要求达标。 2. 根据架构方案完成微架构拆分、接口规格设计，处理跨时钟域、复杂数据通路等关键技术点。 3. 参与 DV、PD、DFT 协同流程，配合完成设计收敛、静态时序分析（STA）与功能验证问题定位。 4. 配合架构团队进行性能建模，支持 Pre-silicon 调试，参与部分 Post-silicon 问题排查。 5. 关注前沿设计方法和 EDA…
数字前端设计工程师
1、架构与方案设计：分析数字芯片需求，细化芯片模块架构与方案设计，撰写设计文档，承担交付职责。 2、AI辅助RTL开发：借助 Claude Code、Codex 等 AI 编码工具，完成核心模块的 RTL 设计与高效代码生成，保障逻辑正确性与可靠性。 3、PPA与时序优化：开展芯片 PPA评估与优化，解决关键时序与性能瓶颈，协助完成 STA。…
Hardware Engineer, RTL
Design and verify digital logic for novel AI hardware using SystemVerilog, collaborating across architecture, verification, and physical design to tape out custom ASICs.
Intern Digital IC Design
Intern designs and verifies low-power digital ICs using SystemVerilog/Verilog, simulates MCUs, and prototypes designs on FPGA.
Manager / Senior Manager – Design Verification
Lead a team to verify low-power wireless SoC designs using SystemVerilog/UVM, ensuring robust IP and chip-level functionality across global projects.
Ingénieur en conception de micrologiciel - Firmware Design Engineer
Designs and implements firmware for high-speed SERDES PHY IP, collaborating on architecture, verification, post-silicon validation, and customer deployment using C/C++ and Python.
Senior Hardware Security Engineer
Design and verify secure hardware for space systems, assess FPGA/ASIC vulnerabilities, and develop guidance to mitigate threats in embedded and cyber-physical systems.
Emulation Front-End Infrastructure Engineer
Engineer scalable compilation and synthesis flows for NVIDIA’s hardware emulation platforms, using EDA tools like Synopsys and Cadence to validate complex chip designs before fabrication.