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Designs and validates advanced analog mixed-signal circuits for next-gen High Bandwidth Memory (HBM) chips, including amplifiers, bandgap references, and IO circuits, using SPICE simulators and layout tools.
Designs and automates AI/ML-driven tools to optimize ASIC chip development for automotive processors and microcontrollers, using Python/C++ and advanced ML techniques.
Leads the design and integration of digital subsystems for Automotive Ethernet PHY products, including PCS logic, safety mechanisms, and system-level validation in a semiconductor environment.
Design verification engineer building and running UVM/SystemVerilog testbenches for AR display ICs using Siemens Questa, plus coverage closure and automation in Linux.
Designs and debugs test logic for ASIC/SoC chips, inserting scan chains and MBIST, and generating ATPG patterns to ensure manufacturability and high fault coverage.
Lead hardware emulation and FPGA prototyping for semiconductor customers, designing advanced verification solutions for high-speed protocols like PCIe and CXL.
Manage CAD flow development and ESD design methodology, integrating ESD protection into electronic designs and leading teams to ensure compliance and efficiency using tools like Cadence Virtuoso and Synopsys Primetime.
Designs and verifies ASIC/FPGA digital architectures and RTL code for defense systems, integrating and testing FPGA modules in a lab using industry-standard tools.
Designs and verifies FPGA hardware using VHDL/Verilog/SystemVerilog, UVM testbenches, and Xilinx tools, while guiding a remote verification team on DO-254 processes.
Note: This position is posted for Markham, but it is open to candidates across Canada, including Mississauga, Nepean, and Ottawa. The role can be hybrid or fully remote depending on your location and preference. We Are…
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Designs and verifies digital circuits for FPGA and ASIC implementations, coding HDL modules and collaborating with cross-functional teams to meet performance and reliability targets.
Leads the design and deployment of networking IP blocks for Google Cloud's custom silicon, using ASIC/SoC methodologies and RTL coding (Verilog/SystemVerilog/VHDL) to deliver high-performance, low-latency hardware solutions.
Leads a hardware design team developing 5G baseband IP for satellite-based base stations, focusing on power efficiency and delivery of Layer 1 IP using RTL, FPGA, and ASIC techniques.
Designs and implements FPGA/ASIC hardware for satellite-based 5G base stations, focusing on signal processing and power efficiency using Verilog/SystemVerilog and EDA tools.
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