Tech jobs

Open 32d On-siteLATAM, North America H-1B sponsor history

SOC Design Verification Engineer– Pre-Si/Post-Si Verification

Company: QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Job Overview We are seeking motivated Engineer and Senior…

AI Automation Bash Cloud C++ +11 skills

weekday-1

ASIC RTL Design Engineer

Open 78d APACFull-time

Asic Rtl SystemVerilog Verilog

Design and implement synthesizable RTL for complex ASICs using Verilog/SystemVerilog, optimizing for power, performance, and area while collaborating with verification and physical design teams.

3M – 5M INR

SiFive

Power Management Design Engineer

Open 78d North America

Confluence Git GitHub Jira Machine Learning +4 skills

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…

Cerebras

Open 103d On-siteNorth AmericaStaff

Senior Staff Design Verification Engineer

Agentic AI AI Automation Ccpa Cloud +9 skills

Design Verification Engineer at Cerebras, building and testing the world's largest AI chip to ensure first-silicon success and ultra-fast AI inference.

250K – 300K $

Advanced Micro Devices, Inc

Open 90d North AmericaInternshipIntern

Design Verification Engineer

Design Verification Engineer at AMD responsible for verifying custom hardware accelerators for servers, datacenters, and client/embedded markets using advanced ASIC verification techniques and methodologies like UVM and formal verification.

Agentic AI AI Authentication Automation ChatGPT +11 skills

Cisco

Open 116d North AmericaFull-time Licensed NL sponsor

ASIC Design Engineer, STA

AI Asic Cisco SystemVerilog Verilog

Design engineer builds and validates static timing analysis flows for Cisco’s unified ASICs, resolving timing closure issues across chip blocks and collaborating with physical design teams.

155K – 223K $

RTX

Open 79d On-siteAPAC, North AmericaFull-timeMiddle

FPGA Engineer II (ONSITE)

Design and verify FPGA/ASIC digital circuits for aerospace/defense avionics, writing RTL in VHDL/Verilog and ensuring DO-254 compliance.

C++ Ethernet FPGA I2c Itar +10 skills

69K – 131K $

Texas Instruments

Open 79d North America Licensed UK sponsor Licensed NL sponsor

Digital and Mixed Signal IC Design/DV Engineer

Automation Rtl SystemVerilog Uvm Verilog +1 skills

Design and verify mixed-signal ICs for current sensing, using RTL, SystemVerilog, VHDL, and UVM to ensure first-pass silicon success.

nexperia

Open 79d North America Licensed UK sponsor Licensed NL sponsor H-1B sponsor history

Mixed Signal Design Verification (MSDV) Engineer

Bash Git I2c Perl Python +7 skills

Designs and verifies mixed-signal ICs, leading pre-tapeout simulations and regressions to ensure silicon meets specs and is manufacturable.

Qualcomm

USB-Design Verification Senior Engineer

On-siteAPACSenior

Firmware FPGA Perl Python REST Assured +3 skills

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to…

Advanced Micro Devices, Inc

Lead CPU Design Verification Engineer

Open 80d APACLead

AI Asic Cloud C++ Go-to-Market +1 skills

Lead the verification of next-gen x86 CPU cores, architecting testbenches and coverage plans for high-performance, low-power processor features in a global team.

Microsoft

Open 80d On-siteAPACMiddle

Design Verification Engineer II

Azure Cloud C++ Perl Python +3 skills

Design verification engineer building and debugging custom silicon for AI hardware using SystemVerilog, UVM, and formal tools.

Positron AI

Open 62d RemoteNorth America

Director of Silicon Validation

AI Asic Automation CI/CD Embedded Software +12 skills

Role Overview We are looking for a Director of Silicon Validation to own the complete verification and validation lifecycle of our AI inference silicon, from pre-silicon functional verification, through hardware…

Northwood Space

Open 81d North AmericaFull-time

FPGA Engineer

C++ FPGA Itar Networking Oscilloscope +6 skills

Design and implement FPGA-based networking and DSP blocks for satellite ground stations, ensuring resilient, high-rate data links for real-time space communications.

100K – 160K $

broadcom

R&D Engineer IC Design 5

Open 80d North America

Asic C++ Ethernet Networking OOP +4 skills

Design and verify high-performance network switch ASICs using SystemVerilog, UVM, and C++, developing complex verification environments and test plans.

144K – 230K $

ARM

Open 80d HybridNorth AmericaSenior Ireland permit employer

Senior Security IP Design Engineer

Accessibility AI Cryptography Firmware Perl +6 skills

Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and SystemVerilog.

162K – 219K $

Quadric

Senior SoC Design Verification Engineer

Open 80d APACSenior

AI Assembly C++ Embedded Systems Neural Networks +5 skills

Leads SoC-level verification for a semiconductor company’s edge AI processor (GPNPU), designing testbenches, verifying subsystems (NoC, PCIe/UCIe, DDR), and ensuring hardware-software co-simulation coverage using UVM, Verilog, assembly, and Python.

Quadric