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NVIDIA 2027 Internships: Hardware Physical Design / VLSI
NVIDIA is seeking interns for 12-week roles in hardware physical design and VLSI, focusing on chip implementation, timing closure, and physical verification using industry-standard EDA tools. Interns will work on projects impacting accelerated computing, AI, and robotics while pursuing their degree.
NVIDIA 2027 Internships: Hardware ASIC Design
NVIDIA is seeking interns for 12-week hardware ASIC design roles, focusing on tasks like RTL design, verification, and physical design. Interns will work on projects impacting AI, robotics, and accelerated computing using tools like SystemVerilog, C++, and Python.
NVIDIA 2027 Internships: Hardware Design for Test (DFT)
NVIDIA is seeking M.S. or Ph.D. students for a 12-week Hardware Design for Test (DFT) internship. Interns will work on hardware testing architectures, digital design, and silicon debug using tools like Synopsys and Cadence.
NVIDIA 2027 Internships: Hardware Engineering
NVIDIA offers 12-week hardware engineering internships for students pursuing degrees in electrical or computer engineering. Interns work on projects across system validation, hardware design, mechanical engineering, and silicon solutions using tools like Python, Verilog, and various CAD software.
IO and Mixed Signal Circuit Design Engineer
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Design Engineer - Flow Development
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Design Engineer - Timing Methodology
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Analog Design, Sr Staff Engineer 18395
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Analog Design, Staff Engineer-18375
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…
Validation Engineer
About the Role We are seeking an experienced System Validation Engineer to join a team responsible for the integration, bring-up, and validation of next-generation System-on-Chip (SoC) products used in data center,…
Senior Staff Front-End Engineer IP Integration
The role develops and integrates PCIe-related IP blocks, evaluates performance, supports verification closure and functional coverage, debugs pre-silicon and post-silicon issues, and contributes to software development…
Senior Staff Front-End Design Engineer RTL Design RISC-V
Integrate commercial RISC-V core soft IP with external accelerators, tailor CPU features to meet performance, power, and area requirements, modify Verilog and SystemVerilog RTL, collaborate across ASIC design…
ASIC Development Engineer Digital IC Design (f/m/div.)
Lead digital ASIC design and ATPG for automotive semiconductors, defining test strategies and improving product quality through scripting and cross-team coordination.
PD Architect
Lead physical design (RTL-to-GDS) for AMD’s next-gen AI and high-performance ASICs, driving PnR, timing closure, and tape-outs while collaborating with architects and EDA vendors.
Experienced RTL Design Engineer (3+ Years of Experience)
Designs and implements RTL for SoC PAD/PFC logic (pin multiplexing, I/O control) using Verilog/SystemVerilog, in-house tools, and automation scripts to ensure design quality and integration.