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Build and maintain UVM/SystemVerilog testbenches to verify PCIe and memory-subsystem RTL, collaborating with architects and post-silicon teams to ensure robust, high-performance designs.
System Design & Failure Analysis Engineer Location: Irvine, CA, us Company Description WD is building the infrastructure behind the AI-driven data economy. As AI scales, so does data. Every interaction, every…
Designs and debugs mixed-signal PCBs and hardware systems, including schematics, layout, bring-up, and signal integrity, using lab tools and communication protocols like I2C/SPI/UART/CAN.
Software Engineer II - Device Drivers Location: Ann Arbor, MI Department: Compute Platform About Torc Torc has been a leader in autonomous vehicle technology since 2007. Now part of the Daimler family, we’re focused on…
Experienced FPGA Developer Location: Rancho Santa Margarita, CA, us Company Description CS Group USA, a subsidiary of CS Group, is a key player in the development and certification of safety-critical systems in the…
Designs and owns the end-to-end system management architecture for NVIDIA SmartNIC cards, defining secure provisioning, reset, and recovery flows across ASICs, BMCs, and CPUs using protocols like MCTP, PLDM, and SPDM.
Designs and implements high-performance memory compilers and RTL blocks for custom SoCs, collaborating with architecture, verification, and physical design teams to deliver silicon-ready IP.
Develops low-level networking platform software for high-performance routing products, focusing on interfaces, optics, and hardware integration in C/C++ on Linux.
Lead hardware board design and system engineering for Cisco’s Edge and Access routing products, shepherding designs from concept through production and validation.
Lead physical design and implementation for complex semiconductor subsystems, driving RTL-to-GDSII flows, floorplanning, place-and-route, and timing closure for high-performance SoCs.
Design and verify FPGA hardware for defense systems using VHDL, targeting AMD/Altera/Microchip devices and collaborating with systems engineers.
Design and verify high-speed digital electronics for missile guidance and signal processing, using FPGAs, processors, and industry interfaces like PCIe and Ethernet.
Designs and validates next-gen Ethernet data center networks for AI and cloud customers, using BGP, VxLAN, EVPN, and Linux automation to optimize GPU-accelerated workloads.
Develops low-level diagnostic software for NVIDIA’s next-gen data center GPUs and AI systems, testing hardware like compute engines, memory, PCIe/NVLink, and thermal/power subsystems via C/C++/Python.
Own the roadmap for PCIe, CXL, and DMA IP within Altera’s FPGA portfolio, gathering requirements from engineering, marketing, and customers to define and prioritize next-gen semiconductor IP solutions.
Lead the integration of custom silicon (SoCs/ASICs) with firmware and software stacks, from pre-silicon planning through lab bring-up and system debugging for a next-gen satellite communications network.
Your Job Molex is seeking a dynamic and proactive Field Application Engineer (FAE) to lead, promote, and resolve all technical and engineering related barriers in designing Molex connectors, cables, and solutions for…
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Designs and implements ASIC/SoC RTL (Verilog/SystemVerilog) for high-performance SSD controllers, collaborating with verification, validation, and firmware teams to deliver next-gen enterprise and AI data center storage solutions.
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