6+ month contract FPGA engineer designing and implementing digital payload code for Kepler's satellites: custom IP, DSP modulation/demodulation for on-board software-defined radios, and embedded processor/peripheral interfaces. Full FPGA flow (simulation, synthesis, place & route, timing closure, hardware testing) using Verilog/SystemVerilog/VHDL on Xilinx Zynq/UltraScale.
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