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An ASIC digital engineer specializing in FPGA prototyping, emulation, and system-level debugging to support platform bring-up, hardware/software co-verification, and end-user collaboration.
Build and optimize AI/HPC middleware (MPI/SHMEM, NCCL/RCCL) for Cornelis’ high-performance networking stack, contributing upstream to open-source projects and collaborating across kernel, switch, and application teams.
The Technical Program Manager will lead cross-functional ASIC and high-speed interface development programs at Cisco, managing the full product lifecycle from concept to production. The role requires coordinating between engineering, architecture, and operations teams to ensure successful delivery of complex silicon solutions.
The Senior ASIC Design Engineer will architect and design high-performance networking ASICs, focusing on micro-architecture, logic design, and power optimization. The role involves collaborating with verification and physical design teams to ensure successful implementation and timing closure.
The Senior ASIC Design Engineer will architect and design high-performance networking ASIC blocks, focusing on micro-architecture, logic design, and power efficiency. The role involves collaborating with verification and physical design teams to ensure successful implementation and timing closure.
The ASIC Design Engineer 2 will work on high-speed networking chips, handling tasks from functional specification to final netlist. The role involves RTL coding, timing closure, and debugging using System Verilog and state-of-the-art EDA tools.
The Systems/Embedded Software Engineer designs and maintains embedded software for ASIC-based products, collaborating with hardware teams to ensure system performance. The role involves using C, Rust, and AI-assisted tools to develop low-level software, debug hardware-software interactions, and lead technical project initiatives.
The ASIC Design Engineer 2 will contribute to the development of high-speed networking chips by performing RTL coding, micro-architecture specification, and timing closure. This role involves working with state-of-the-art EDA tools to design and debug complex silicon modules for routers and switches.
The Systems/Embedded Software Engineer designs and maintains embedded software for ASIC-based products, collaborating with hardware teams to ensure system performance. The role involves using C, Rust, and AI-assisted tools to develop low-level components and debug complex hardware-software interactions.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Sr. Staff ASIC Design Engineer responsible for microarchitecture and RTL design of high-performance AI inference ASICs using Verilog/SystemVerilog, integrating CPU and third-party IPs, and collaborating with physical design and verification teams.
The Junior ASIC Test Engineer will work in a laboratory environment to test and characterize complex ASICs, investigate performance issues, and collaborate with design engineers. This role is suitable for recent engineering graduates or professionals with early-career experience in electronics testing.
Junior engineer builds and runs test environments to verify next-gen AI connectivity chips using SystemVerilog/UVM and debugs hardware issues with design teams.
Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.
Senior engineer builds and runs test environments to verify high-performance AI connectivity chips using SystemVerilog/UVM, ensuring flawless silicon for next-gen data centers.
Leads end-to-end execution of advanced-node ASIC products from concept to production, managing schedules, budgets, and cross-functional teams to deliver revenue-critical silicon on time and at scale.
Leads the full lifecycle of ASIC chip development for AI infrastructure, coordinating cross-functional teams to design, fabricate, and validate semiconductor solutions.
Principal Architect at Astera Labs in Tel Aviv designs high-performance AI connectivity solutions, focusing on PCIe, Ethernet, and advanced interconnect protocols like CXL and UALink.
Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.
Designs and implements digital blocks for semiconductor chips powering AI infrastructure, using Verilog/SystemVerilog and RTL coding principles with industry EDA tools.
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