Solution Validation Engineer at AMD (San Jose) who designs, verifies, and validates FPGA/SoC hardware-software solutions end to end: RTL in SystemVerilog/Verilog, embedded Linux via Yocto, Vivado/Vitis integration, board bring-up, and pre/post-silicon validation for interfaces like PCIe Gen6/7, LPDDR5/6, and other high-speed I/O across networking, automotive, aerospace, and AI/ML workloads.
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