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Design and implement FPGA/ASIC applications using OCaml and Hardcaml (an OCaml RTL library) for RTL design and testing, with some Verilog and C work, at a quantitative trading firm.
Interns collaborate with full-time engineers on FPGA/ASIC hardware projects using OCaml and Hardcaml, from design to validation, with mentorship and exposure to Jane Street’s internal tools.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Senior engineer leading FPGA system-level design creation, lab bring-up (60% of time), and validation for Microchip's semiconductor products, using Verilog/VHDL, C, and high-speed serial protocol expertise.
The Lead RTL Design & Validation Engineer will plan and execute the design and validation of DDR memory controller calibration solutions, including RTL logic and firmware routines. The role involves collaborating with cross-functional teams to ensure reliable memory initialization and performance across AMD's custom IP projects.
Develops FPGA/emulation models and tools for Pre-Si hardware/software verification, optimizing test environments and debugging RTL for Intel’s Pre-Silicon validation and Post-Silicon validation.
Lead Digital IP and subsystem development programs at NXP Semiconductors from planning through SoC integration release, driving cross-functional execution across architecture, design, and verification teams while building dashboards and metrics with tools like Power BI, SQL, and Jira.
Join Solidigm’s visionary Design Engineering Team as a 3D NAND IP Logic Design Engineer and help shape the future of memory technology. Job responsibilities include, but not limited to: Architect, design, and verify…
Design and verify custom ASICs for ultra-low-latency trading systems using SystemVerilog, C++, and Python, collaborating with hardware, software, and trading teams.
Design and optimize CPU architecture and microarchitecture features for Google's custom SoCs powering consumer products, focusing on performance modeling, ISA development, and cross-team collaboration using C/C++ and Python.
NextSilicon is reimagining high-performance computing (HPC & AI). Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new…
Senior Staff SOC DFX RTL Design Engineer at AMD's Radeon Technologies Group responsible for planning and implementing DFX features (JTAG, Scan, Boundary Scan, Debug) for next-generation microprocessors, collaborating with architecture, IP design, and physical design teams.
Leads a team designing high-performance, low-power System-on-Chip (SOC) components using Verilog/System Verilog, UPF, and industry-standard EDA tools.
RTL/SOC integration design engineer at AMD Hyderabad, responsible for ASIC design in sub-20nm nodes using Verilog/SystemVerilog, timing analysis, low-power design, and SOC verification tools.
Principal Digital Design Engineer owning the architecture and RTL development of a configurable IO subsystem for onsemi's microcontroller platform, using SystemVerilog, Python-based design generators, and UVM verification in Allen, TX.
The Senior ASIC Design Engineer will architect and design high-performance networking ASICs, focusing on micro-architecture, logic design, and power optimization. The role involves collaborating with verification and physical design teams to ensure successful implementation and timing closure.
The Senior ASIC Design Engineer will architect and design high-performance networking ASIC blocks, focusing on micro-architecture, logic design, and power efficiency. The role involves collaborating with verification and physical design teams to ensure successful implementation and timing closure.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Overview As a Senior Principal Design Engineer, you will be responsible for the design,…
Design Intern at Microchip's Data Center Solutions unit writing RTL (Verilog/SystemVerilog) for storage controller SOCs and developing AI-based tools and automated design flows to enhance productivity.
Job Description: 1. Responsible for micro-architecture design and RTL implementation of high-performance CPU front-end pipeline, including instruction fetch, branch prediction, instruction decode, dispatch and…
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