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Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Minimum 2 to 4 years of work experience in ASIC RTL Design Experience in Logic…
Job Details: Job Description: GPU Senior Logic Design Engineer: Develop logic design, generate/write Register Transfer Level (RTL) code, and perform simulation for Media IP components. This includes generating…
Job Details: Job Description: Intel is seeking an experienced Logic Design engineer for the Intel Chassis Group, which is chartered to deliver the chassis for SoCs within Intel. The role involves logic design of…
Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment,…
Staff Engineer, Design Verification - High-Speed Interface IP We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver…
Job Overview: We’re looking for a passionate Staff Hardware AI Engineer to join our team. You will build AI-enabled automation that makes Arm digital hardware design & verification engineers drastically improve…
Arm CPUs are everywhere, from the devices in your pocket to laptops, servers and increasingly AI and infrastructure systems! If you are interested in how those processors are designed and optimised at the…
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering ( SCHIE ) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
Senior firmware/FPGA engineer at LHP Engineering Solutions in Goleta, CA, designing low-level firmware and RTL logic (Verilog/VHDL) for safety-critical automotive systems, running RTL simulation/formal verification and IV&V, and producing ISO 26262-compliant safety work products for automotive and transportation customers.
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
Designs and implements high-performance ASIC blocks for an AI accelerator, using SystemVerilog and industry protocols like AXI and PCIe.
Designs high-performance, power-efficient digital chips for AI inference at Fractile, focusing on RTL development and cross-functional collaboration.
Senior/Principal Physical Design Engineer at Fractile, responsible for end-to-end ASIC/SoC physical design implementation (floorplanning, placement, CTS, routing, sign-off) using EDA tools like Cadence Innovus, Synopsys Fusion Compiler, and Mentor Graphics Calibre, optimizing PPA metrics and collaborating with cross-functional teams.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Design and verify custom ASICs for ultra-low-latency trading systems using SystemVerilog, C++, and Python, collaborating with hardware, software, and trading teams.
Senior design verification engineer on Google's custom silicon team, verifying ASIC blocks that power consumer hardware (mobile image and AI processing). Day to day: planning verification from architectural specs, building SystemVerilog/UVM testbenches, formal verification with SVA, driving coverage closure, and debugging designs with RTL engineers through tape-out.
Join CERN's EP-ESE-ME section in the development of a radiation-tolerant microcontroller ASIC for use in future particle physics detectors and accelerator systems. Operating in highly challenging radiation…
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML…
Google is hiring a Senior Technical Program Manager in Tel Aviv or Haifa to orchestrate chip DevOps: scaling EDA toolchains and cloud compute grids and driving a unified silicon design/verification methodology in partnership with Design, Verification, CAD, and Infrastructure teams.
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