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Physical Design Engineer - Block Level, Subsystem Implementation
Designs and optimizes AI hardware blocks from RTL to GDSII, focusing on PPA and timing closure for high-performance inference chips.
Manager / Senior Manager – Design Verification
Lead a team to verify low-power wireless SoC designs using SystemVerilog/UVM, ensuring robust IP and SoC solutions for edge connectivity applications.
[India] Physical Design Lead
Lead the physical design of AI SoCs and chiplets from RTL to GDSII, optimizing power, performance, and area using Synopsys/Cadence tools and guiding external partners.
Lead Software Engineer
Lead a global R&D team to design, develop, and debug software for the Innovus Implementation System, a physical design tool for ICs, using C/C++ in Linux and collaborating with customers.
Design Verification Engineer
Design Verification Engineer at AMD responsible for developing and maintaining tests to verify complex processor architectures and ASIC/SOC designs using Verilog, SystemVerilog, and UVM.
Design Verification Engineer
Designs and validates FPGA acceleration frameworks using SystemVerilog/UVM to verify embedded, data center, and communication IP blocks.
Senior Staff Engineer, Physical Design (Floorplanning)
Senior engineer leading physical design and floorplanning for high-performance GPUs and SoCs at advanced technology nodes, optimizing power, performance, and area while mentoring peers and driving EDA/tool innovation.
Embedded Software Development Engineer in Test (Embedded SDET) - Nottingham, UK
Imagine yourself… Growing your expertise and expanding your technical skillset with every project. Solving complex engineering challenges that help bring innovative products to life. Thriving in a collaborative team…
ASIC Digital Design, Staff Engineer - 18270
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
DFT Design Engineer
Designs and implements automated test and debug features for AMD's complex processor and GPU chips, using scripting and AI/ML tools to improve chip reliability and performance.
ASIC Design Engineer — IP Integration & Implementation
Designs and integrates high-performance, low-power pixel processing ASICs for Apple’s SoCs, collaborating across teams to deliver functional multimedia IP for millions of devices.
Инженер - программист ПЛИС / FPGA Designer
FPGA engineer designs, tests, and integrates Verilog-based image-processing IP cores and high-speed interfaces for embedded systems in an on-site Moscow role.