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Lead hardware design engineer building electronic systems and products across sectors like defence, healthcare, and consumer tech, from concept to deployment.
Leads verification strategy for next-gen semiconductor interconnect products, building UVM/SystemVerilog testbenches and driving silicon success for high-speed digital designs.
Designs and debugs FPGA firmware for high-speed RF/wireless systems, including DSP, JESD204C, and 100G Ethernet, using VHDL/Verilog and Python/C/C++.
Design and implement high-performance embedded RF systems and distributed C++ architectures for real-time signal processing, integrating across x86, ARM, and FPGA domains.
Designs and validates high-performance digital circuits (FPGA/ASIC) and embedded software for aerospace/defense projects, using VHDL/Verilog and tools like Altium/Cadence.
Design and validate complex FPGA/SOC systems for critical aeronautics applications using VHDL/Verilog, ensuring compliance with DO-254 and collaborating with hardware/software teams.
Design and validate complex FPGA/SOC designs for critical aerospace systems using VHDL/Verilog and industry tools, ensuring compliance with safety standards.
Ingénieur en électronique - SPATIAL (H/F) Location: Toulouse, Occitanie, fr Description de l'entreprise Avec plus de 30 ans d’histoire, ALTEN accompagne en France et dans le monde entier la stratégie de…
Internship in hardware acceleration for high-performance financial systems, working with GPU/FPGA solutions and heterogeneous computing under expert guidance.
Designs and verifies high-speed interconnect protocols (PCIe, CXL, AXI) using UVM and SystemVerilog to ensure ASIC/subsystem correctness before tape-out.
Lead RTL design for audio hardware at Qualcomm, optimizing circuits and collaborating with cross-functional teams to deliver cutting-edge chipsets for mobile and embedded systems.
Designs and optimizes System-on-Chip (SoC) architectures for mobile/IoT/XR platforms, focusing on performance, power, and security trade-offs.
Designs low-power analog PLL/DLL/LDO and data-converter IPs for Qualcomm SoCs, using SPICE, Virtuoso, and FinFET processes.
Develop and validate firmware for Qualcomm’s IP blocks, debug hardware-software interactions, and collaborate with design teams to ensure silicon performance and reliability.
Design and optimize the physical layout of high-speed CPU cores, ensuring timing closure and power-performance-area targets for next-gen Qualcomm chips.
Design and optimize hardware circuits for Qualcomm’s next-gen chips, using simulation tools and lab instruments to validate performance and yield.
Design verification engineer building UVM testbenches and test plans for USB controllers (USB3.2, USB2.0) to ensure compliance with industry standards.
Senior PWB Designer creates high-density circuit boards for mobile, modem, and IoT devices using Mentor Xpedition, PADS, and Cadence Allegro.
Design Verification Engineer at Qualcomm verifies Bluetooth chipset designs using SystemVerilog/UVM, formal checks, and emulation to ensure hardware meets specifications before production.
Designs and tests PMIC hardware systems, including digital/analog/RF circuits, using tools like oscilloscopes and simulation software to validate performance and yield for Qualcomm’s next-gen chips.
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