Senior physical design role on NXP's new Catania MCU team, implementing complex high-performance chips day to day: floorplanning, power grid, place and route, clock tree synthesis, static timing closure, power/signal integrity, and physical verification (DRC/LVS) with EDA tools like Cadence Innovus, Synopsys ICC2/PrimeTime, and Ansys RedHawk, plus mentoring junior engineers.
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