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Leads cross-functional ASIC development programs from planning through tapeout, coordinating RTL design, verification, physical design, and external partners to deliver custom silicon for AI infrastructure.
Leads a team to design test strategies for high-speed PCIe switch chips using advanced 2.5D/3D packaging, ensuring manufacturability and quality for AI infrastructure components.
Leads ASIC design for AI infrastructure connectivity, focusing on Ethernet, PCIe Gen 6/7, and UALink. Sets technical direction, mentors engineers, and drives hardware/software integration for high-speed networking and AI interconnects.
Lead ASIC design for high-speed Ethernet and AI interconnect fabrics, defining architecture and RTL for controllers, NICs, and packet processing pipelines to enable rack-scale AI infrastructure.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
About Bitdeer Technologies Group Bitdeer is a world-leading technology company for AI and Bitcoin mining infrastructure. Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers and…
Designs and verifies next-gen ASIC/FPGA SoCs using SystemVerilog/UVM, ensuring bug-free silicon by collaborating across global teams.
Main Supervisor: Dr. Edmond Cretu, Department of Electrical & Computer Engineering, UBC Duration: 2 years Who We Are: Sonus Microsystems and the AdaMist (Adaptive Microsystems) research group at UBC, led by Dr.…
Drive post-silicon productization of bitcoin mining ASICs from bring-up through mass production, developing ATE test programs, optimizing yield, and performing silicon data analysis across cross-functional teams.
THE ROLE: You will plan, develop, and execute the SoC verification of new and existing features for AMD’s ASIC and FPGA SoCs, ensuring there are no bugs in the final design. THE PERSON: You have a passion for…
The Principal Engineer leads SSD system design and architecture from concept through high-volume manufacturing. This role drives system definition, characterization strategies, and cross-functional execution to deliver…
Avanti Recruitment is working with an established technology company looking for a Junior ASIC Test Engineer to join its R&D team. You’ll work in a hands-on laboratory environment, testing and characterising…
ASIC Design Engineer This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard
The ASIC Design Engineer will design, simulate, and test VLSI components and computer architectures using EDA and FPGA tools. This onsite role involves collaborating with engineering teams to develop reliable, high-quality hardware solutions.
Principal FPGA Engineer at a photonic AI compute startup, writing and deploying RTL (Verilog/VHDL) and embedded C/C++ to FPGAs for chip verification and prototype development, fully onsite in Boston.
Senior FPGA Engineer writing and deploying RTL (Verilog/VHDL) and embedded C/C++ to FPGAs for chip verification and prototype development of photonic AI processors.
Senior Technical Recruiter owning full-lifecycle hardware recruiting (Design Verification, ASIC, physical design, PCB/systems) at an AI chip company, using Greenhouse ATS and sourcing via LinkedIn and GitHub.
Apple is offering GPU internships in the UK focused on RTL design, power optimization, and physical design for Apple Silicon. Interns will collaborate with engineering teams on chip architecture, power analysis, and ASIC design flows using languages like C++, Python, and Verilog.
Designs and verifies complex ASICs for Google’s TPU hardware, focusing on AI/ML acceleration in data centers. Uses SystemVerilog/UVM to test digital logic, debug designs, and ensure functional correctness for next-gen data center accelerators.
Design analog and full-custom CMOS modules for mixed-signal ASICs used in semiconductor test equipment, taking designs from concept through silicon to production in a global engineering team.
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