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Validates NPU SoC hardware for FuriosaAI, ensuring first-silicon bring-up, system-level debugging, and performance optimization across AI compute components like NPU cores, CPUs, and high-speed interfaces.
Designs and optimizes AI hardware architectures, focusing on performance, power, and area (PPA) metrics. Uses Verilog, EDA tools, and scripting to perform synthesis, equivalence checking, and timing analysis for chip-level designs.
Hardware Design Verification Engineer at FuriosaAI responsible for defining and implementing verification plans, building test benches, and debugging design failures using SystemVerilog/UVM methodologies and EDA tools.
Principal Hardware Engineer designing and validating high-end routing platforms, collaborating with cross-functional teams on PCB design, signal integrity, power, and thermal considerations for mass production.
VLSI Design Engineer responsible for designing cutting-edge communication systems from scratch, including micro-architecture definition, RTL coding in Verilog/SystemVerilog, synthesis, timing analysis, and PPA optimization, collaborating closely with verification, DFT, and physical design teams.
The FPGA Developer will design, implement, and test high-performance RTL for low-latency high-frequency trading strategies. The role requires expertise in VHDL/Verilog, FPGA debugging tools, and collaboration with software teams to optimize trading system performance.
The Physical Design Engineer II is responsible for the end-to-end physical implementation of semiconductor designs, including netlist to GDSII, timing signoff, and floor planning. The role requires expertise in PnR tools like Synopsys ICC/ICC2 or Cadence Innovus and experience with advanced process nodes.
The Physical Design Engineer is responsible for the end-to-end implementation of chip designs, from netlist to GDSII, including floor planning, timing signoff, and clock tree synthesis. The role requires expertise in industry-standard EDA tools like Synopsys ICC/ICC2 or Cadence Innovus and experience with advanced process nodes.
The Design Verification Engineer will develop verification environments, test plans, and perform functional RTL testing at the IP and SoC levels. The role requires expertise in ASIC verification methodologies, SystemVerilog, and various communication protocols.
Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve…
Faszinierendes schaffen: Ihre Aufgaben Funktionale Nachweisführung und Verifikation von Luftfahrtprodukten (SW, PLD/FPGA) durch Test und Analyse Festlegung der Anforderungen für Embedded Software- und PLD/FPGA-Tests…
Your responsibilities Functional verification of an Aerospace product (PLD/FPGA) by test and analysis Definition of requirements of PLD/FPGA test and its test equipment Verification and evaluation of verification data…
Faszinierendes schaffen: Ihre Aufgaben • Funktionale Verifikation eines Luft- und Raumfahrtprodukts (PLD/FPGA) durch Tests und Analysen • Definition der Anforderungen für PLD/FPGA-Tests und deren Testumgebung •…
Faszinierendes schaffen: Ihre Aufgaben Functional verification of an Aerospace product (PLD/FPGA) by test and analysis Definition of requirements of PLD/FPGA test and its test equipment Verification and evaluation of…
Job Overview Manages quality functions at the site level, focusing on maintaining high-quality standards, practices, and works closely with TCL roles to support technical quality initiatives. Job Requirements…
Description We are building an intelligent analog and mixed-signal design automation flow that applies agentic AI and machine learning to modernize design and verification practice. You will join a central engineering…
Sr. Design Automation Engineer (AMS Flow Automation & Methodology) We are seeking an AMS Flow Automation & Methodology Engineer to build and deploy scalable verification methodologies for analog and…
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