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Designs and implements digital blocks for semiconductor chips powering AI infrastructure, using Verilog/SystemVerilog and RTL coding principles with industry EDA tools.
Engineer firmware for CXL Smart Memory Controllers, debugging and validating memory subsystems on customer platforms using C and Python, and providing technical guidance to hyperscalers and OEMs.
Leads a team to verify complex semiconductor designs for AI infrastructure, focusing on PCIe, CXL, and UVM methodologies to ensure silicon success.
Leads a team to verify next-generation AI infrastructure SoCs using UVM, formal methods, and emulation, ensuring first-pass silicon success for complex designs in compute and networking.
Leads post-silicon engineering programs for AI connectivity ASICs, coordinating silicon bring-up, validation, and manufacturing release across cross-functional teams.
Leads cross-functional ASIC development programs from planning through tapeout, coordinating RTL design, verification, physical design, and external partners to deliver custom silicon for AI infrastructure.
Leads validation and characterization of advanced photonic integrated circuits (PICs) integrated with electronic ICs for high-speed data center and AI applications, using optical and electrical testing tools.
Designs high-performance digital IP for AI connectivity chips, focusing on RTL, synthesis, and integration of processor and peripheral IPs at advanced semiconductor nodes.
Leads SoC design for high-performance connectivity chips, owning RTL, synthesis, timing closure, and pre/post-silicon debug at advanced process nodes using Synopsys/Cadence tools.
Leads timing closure and sign-off for high-speed connectivity ASICs at Astera Labs, using advanced STA tools and methodologies for 7nm+ SoCs in AI infrastructure.
Designs and runs tests to validate high-speed semiconductor chips (CXL, PCIe, Ethernet) for AI infrastructure, ensuring reliability and performance in server/storage systems.
Leads a team to design test strategies for high-speed PCIe switch chips using advanced 2.5D/3D packaging, ensuring manufacturability and quality for AI infrastructure components.
Lead embedded firmware development for analog and Ethernet connectivity devices, writing C/C++ code for calibration, link management, and hardware bring-up in a fast-moving AI infrastructure startup.
The Firmware Engineer Tech Lead will architect and develop firmware for SoC and system products, focusing on connectivity solutions for AI infrastructure. The role involves implementing key product features, collaborating with hardware teams, and engaging directly with customers.
Senior Sourcing Specialist in Taipei manages procurement, supplier relations, and purchasing for Astera Labs' Asia operations, including lab equipment, facilities, and office needs across multiple cities.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Leads a team to design and tape out advanced multi-die switching chips for AI infrastructure using UCIe, UALink, and PCIe Gen 6/7 in 7nm or smaller process nodes.
Principal Analog Design Engineer at Astera Labs designs high-performance analog and mixed-signal circuits for AI connectivity hardware in San Jose, CA.
Senior Program Manager, HR Operations at Astera Labs manages global immigration programs and HR operations for a high-growth AI infrastructure company, ensuring compliance and scalable processes.
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