Tech jobs

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Senior Engineer - Frontend CAD

On-siteAPACSenior

India

Build and optimize front-end CAD methodologies and verification flows for Ericsson’s 5G/6G ASICs and FPGAs using SystemVerilog/UVM, EDA tools, and CI pipelines, with a focus on AI-driven automation.

Sandisk

Advanced Micro Devices, Inc

Staff high speed datapath and circuit design engineer, VLSI Design Engineering

APACStaff

South Korea

Designs high-speed datapath and circuit blocks for 3D NAND flash memory, including page buffers and RTL logic, using Verilog and simulations to meet performance specs.

verilog

Staff Design Verification Engineer

APACStaff

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Design verification engineer building and running SystemVerilog/UVM testbenches to validate DDR5, LPDDR5/6, and DFI memory interfaces for AMD’s server products.

Rambus

Open 54d APAC H-1B sponsor history

MTS Logic Design

India

Designs high-speed memory interface chips using Verilog/SystemVerilog, working with RTL, ASIC flows, and post-silicon validation to optimize data speed and security.

ai verilog

Velaura AI

RTL Designer – Physical AI Compute

On-siteNorth America

Design and optimize RTL for AI-focused System-on-Chip components, focusing on performance, power, and area while collaborating on verification and physical design.

ai systemverilog verilog

Micron Technology

Circuit / Memory Design Engineer

North AmericaFull-time

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Designs and validates next-gen memory circuits (HBM) using TSV stacking, CMOS, and SPICE simulations to optimize power, speed, and manufacturability for AI/ML workloads.

Micron Technology

Digital Design Engineer, HBM

North AmericaFull-time

ai cad systemverilog verilog

Design and verify high-bandwidth memory (HBM) digital logic using Verilog/SystemVerilog, collaborating with verification and physical-design teams to ensure robust closure and post-silicon debug.

ASX Limited

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Principal FPGA Engineer - Markets Technology

HybridAPACPrincipal

Australia

Senior FPGA engineer designing ultra-low-latency hardware accelerators for an exchange’s trading platform, setting standards and mentoring teams.

Intuitive

FPGA Designer

North America

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Design and implement FPGA firmware for surgical robotics using System Verilog, focusing on video processing, motor control, and high-speed comms, then integrate and validate the designs in Intuitive’s robotic systems.

Microsoft

Open 23d On-siteNorth AmericaFull-timePrincipal

Principal AI Silicon Architect

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Principal AI Silicon Architect designs and optimizes hardware architectures for AI workloads, collaborating with software and hardware teams to deliver high-performance, scalable cloud infrastructure at Microsoft.

142 800 – 274 800 $

Virtu Financial

cpp fpga python systemverilog verilog

FPGA Engineer Intern

EuropeInternshipIntern

Ireland

Build ultra-low-latency FPGA/ASIC components for a global market-making engine, coding in SystemVerilog and Python and seeing designs run on real hardware.

NVIDIA

Manager, DFT - Post Silicon

MENA

Israel

We are looking for a Chip Design DFT/Post Silicon Manager to develop the next generation DFT technologies. As a Chip Design DFT/Post Silicon Manager in the DFT team at NVIDIA, you will lead team that transfer our DFT…

verilog

asx

HybridAPACPart-timePrincipal

Principal FPGA Engineer - Markets Technology

Australia

Lead FPGA design and hardware acceleration for low-latency trading systems, defining architectures for market connectivity and protocol processing to optimize performance and deterministic behavior.

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JOBLINE RESOURCES PTE. LTD.

Senior / FPGA Firmware Engineer (Ref 26545a)

APACSenior

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Designs and maintains FPGA firmware, RTL modules, and device drivers while optimizing performance and debugging hardware-software integration for signal-processing systems.

Advanced Resource Managers Limited

embedded-software fpga verilog

Lead Firmware Engineer

UKContractLead

United Kingdom

Leads firmware development for FPGA-based systems, capturing requirements, designing and verifying hardware logic, and integrating with embedded software and PCB designs.

88 – 88 £ / hr

Elix Sourcing Solutions Limited

cadence-virtuoso python verilog

Analog IC Design Engineer

EuropeFull-time

Ireland

Design and verify analog/mixed-signal ASICs from architecture to silicon validation, collaborating with layout and test teams using Cadence Virtuoso.

up to 110 000 £

MAXLINEAR ASIA SINGAPORE PRIVATE LIMITED

SOC Design Engineer

APAC

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Designs and verifies digital logic for SoCs using VHDL/Verilog, ensuring low-power compliance and DFT readiness, with FPGA prototyping and silicon validation.

ADVANCED MICRO DEVICES (SINGAPORE) PTE LTD

Staff Design Verification Engineer

APACStaff

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Design verification engineer building and running SystemVerilog/UVM testbenches for DDR5/LPDDR5 memory interfaces and DFI protocols in AMD’s server products.

ADVANCED MICRO DEVICES (SINGAPORE) PTE LTD

Principal Staff Silicon Design Engineer - DDR Verification

APACPrincipal