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Mixed Signal Design Verification (MSDV) Engineer
Designs and verifies mixed-signal ICs, leading pre-tapeout simulations and regressions to ensure silicon meets specs and is manufacturable.
Lead CPU Design Verification Engineer
Lead the verification of next-gen x86 CPU cores, architecting testbenches and coverage plans for high-performance, low-power processor features in a global team.
Staff DFx Methodology Architect
Architect and implement DFx (Design for Test, Debug, etc.) methodologies and RTL for AMD’s AI-focused SoCs and ASICs, ensuring power, performance, and timing targets while collaborating across global teams.
Staff Electrical and Electronic Design Engineer - Future Forward
The Future Forward group within Intuitive Surgical is searching for a Staff Electrical and Electronic Design Engineer to architect, design, and bring up the electronic hardware behind next-generation robotic and vision…
Principal Silicon Design Verification Manager
Leads a silicon engineering team to design and verify complex security-focused subsystems for Windows client products, blending hands-on verification (SystemVerilog/UVM, Python) with team mentorship and AI-driven workflow improvements.
FPGA Engineer
Develop FPGA-based digital designs for thermal cameras used in drones and navigation systems, implementing RTL in VHDL/Verilog and Ethernet protocols.
Design Verification Engineer II
Design verification engineer building and debugging custom silicon for AI hardware using SystemVerilog, UVM, and formal tools.
Senior FPGA Engineer - Chesterton
Design and build real-time FPGA-based hardware systems using SystemVerilog/VHDL, PCIe, and Ethernet in a fast-growing Cambridge startup.
FPGA Emulation Engineer
Build and debug FPGA-based emulation platforms (Synopsys HAPS) to validate complex SoC/ASIC designs and enable early software execution before silicon tape-out.
FPGA Engineer
Design and implement FPGA blocks for high-rate data transport and signal processing in satellite ground stations, using Verilog/SystemVerilog and Python.
FPGA Engineer
Design and implement FPGA-based networking and DSP blocks for satellite ground stations, ensuring resilient, high-rate data links for real-time space communications.
Power Management Design Engineer
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…
SoC Verification Architect / SoC TB Architect
Leads verification architecture for complex SoCs using SystemVerilog/UVM, driving tape-out readiness for advanced compute subsystems like GPUs and AI accelerators.
RTL Design
Design and implement RTL for next-gen ASICs using Verilog/SystemVerilog, optimizing for performance, power, and area while collaborating with cross-functional teams.
RTL Micro Architect Lead
Lead RTL design and microarchitecture for high-performance SoC subsystems like GPUs and AI accelerators, optimizing for PPA while guiding cross-functional teams.
SoC Verification Architect / SoC Testbench Architect
Designs and leads verification architecture for complex SoCs with GPU, DSP, and AI accelerators using SystemVerilog, UVM, and coverage-driven methods.
R&D Engineer IC Design 5
Design and verify high-performance network switch ASICs using SystemVerilog, UVM, and C++, developing complex verification environments and test plans.
Security IP Design Engineer
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and SystemVerilog.
Senior SoC Design Verification Engineer
Leads SoC-level verification for a semiconductor company’s edge AI processor (GPNPU), designing testbenches, verifying subsystems (NoC, PCIe/UCIe, DDR), and ensuring hardware-software co-simulation coverage using UVM, Verilog, assembly, and Python.