Backend Engineer Synthesis/DFT/STA
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Summary
Backend IC design engineer at Amlogic (Jurong East, Singapore) doing RTL-to-gate synthesis, SDC constraints, Design-for-Test (scan insertion, ATPG, MBIST, boundary scan), and STA/timing closure for advanced SoC development, working with Synopsys EDA tools alongside physical design teams.
Location: Jurong East, Singapore
Employment Type: Full-time
Openings: 1
About the Role: We are seeking a highly motivated Backend Engineer – Synthesis/DFT/STA to join our growing semiconductor engineering team. The successful candidate will play a key role in backend design implementation, Design-for-Test (DFT), and timing closure activities for advanced IC development.
Key Responsibilities: 1. Responsible for synthesis from RTL to gate-level netlist. 2. Collaborate with the RTL design team to create, validate, and maintain SDC constraints. 3. Work closely with Physical Design (PnR) engineers to optimize power, performance, and area (PPA) of digital modules. 4. Handle DFT (Design for Test) implementation for chip-level and module-level designs, including: - Logic synthesis - Scan insertion - ATPG generation - MBIST implementation - Boundary scan - Functional testing 5. Partner with front-end and back-end teams to perform DFT-related STA, power, and IR-drop analysis, ensuring successful timing closure and design sign-off.
Qualifications: - Bachelor's degree or above in Microelectronics, Electronic Engineering, Computer Engineering, or a related discipline. - Solid understanding of backend IC design flow and methodologies. - Hands-on experience with EDA tools such as Synopsys Design Compiler (DC), Fusion Compiler (FC), and TetraMAX is preferred. - Experience in physical implementation and physical verification of large-scale chips at 28nm technology node or below. - Proficiency in Verilog, TCL, Perl, and Python is an advantage. - Strong analytical, problem-solving, communication, and teamwork skills. - Ability to work effectively in a dynamic cross-functional environment.
Why Join Us - Opportunity to work on cutting-edge semiconductor technologies. - Collaborative and innovative engineering culture. - Exposure to advanced ASIC/SoC development projects. - Competitive compensation and career growth opportunities.
How to Apply: Interested candidates are invited to submit their application through LinkedIn or email their resume to: (HIDDEN TEXT)
We look forward to hearing from talented engineers who are passionate about advanced chip design and verification.
#Semiconductor #ASIC #BackendEngineer #DFT #STA #RTL #PhysicalDesign #VLSIJobs #EngineeringCareers #Hiring #ChipDesign #Microelectronics #LinkedInJobs
About the Role: We are seeking a highly motivated Backend Engineer – Synthesis/DFT/STA to join our growing semiconductor engineering team. The successful candidate will play a key role in backend design implementation, Design-for-Test (DFT), and timing closure activities for advanced IC development.
Key Responsibilities: 1. Responsible for synthesis from RTL to gate-level netlist. 2. Collaborate with the RTL design team to create, validate, and maintain SDC constraints. 3. Work closely with Physical Design (PnR) engineers to optimize power, performance, and area (PPA) of digital modules. 4. Handle DFT (Design for Test) implementation for chip-level and module-level designs, including: - Logic synthesis - Scan insertion - ATPG generation - MBIST implementation - Boundary scan - Functional testing 5. Partner with front-end and back-end teams to perform DFT-related STA, power, and IR-drop analysis, ensuring successful timing closure and design sign-off.
Qualifications: - Bachelor's degree or above in Microelectronics, Electronic Engineering, Computer Engineering, or a related discipline. - Solid understanding of backend IC design flow and methodologies. - Hands-on experience with EDA tools such as Synopsys Design Compiler (DC), Fusion Compiler (FC), and TetraMAX is preferred. - Experience in physical implementation and physical verification of large-scale chips at 28nm technology node or below. - Proficiency in Verilog, TCL, Perl, and Python is an advantage. - Strong analytical, problem-solving, communication, and teamwork skills. - Ability to work effectively in a dynamic cross-functional environment.
Why Join Us - Opportunity to work on cutting-edge semiconductor technologies. - Collaborative and innovative engineering culture. - Exposure to advanced ASIC/SoC development projects. - Competitive compensation and career growth opportunities.
How to Apply: Interested candidates are invited to submit their application through LinkedIn or email their resume to: (HIDDEN TEXT)
We look forward to hearing from talented engineers who are passionate about advanced chip design and verification.
#Semiconductor #ASIC #BackendEngineer #DFT #STA #RTL #PhysicalDesign #VLSIJobs #EngineeringCareers #Hiring #ChipDesign #Microelectronics #LinkedInJobs