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Develops autonomous agent systems that solve complex engineering problems via AI-driven exploration, optimization, and self-improvement, integrating LLM post-training and multi-agent workflows for production-grade solutions.
FuriosaAI is seeking a Software Engineer to develop AI reference applications and maintain internal services to support their AI-native compute platform. The role involves building RAG and agentic systems, creating sample code, and collaborating with the global developer community.
Builds and optimizes an agent system framework for AI-driven automation, integrating LLM-based reasoning, tool execution, and orchestration in a production environment.
About FuriosaAI FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea…
FuriosaAI is seeking a Senior Software Engineer to design and implement the low-level runtime stack for their NPU hardware. The role involves developing firmware, optimizing asynchronous execution pipelines, and enabling multi-node inference using Rust, C, or C++.
Build and optimize a high-performance inference engine for LLMs and multimodal models on FuriosaAI’s NPUs, collaborating with compiler and hardware teams to maximize throughput and efficiency.
Designs and implements enterprise-wide security infrastructure under Zero Trust principles, including policy, access control, cloud security, and incident response for an AI hardware startup.
Leads silicon validation for NPU SoC chips, ensuring system-level functionality from first silicon bring-up to performance optimization and stability. Bridges hardware (RTL/DV) and software (firmware/OS) teams with structured validation processes, debugging, and test automation.
Validates NPU SoC hardware for FuriosaAI, ensuring first-silicon bring-up, system-level debugging, and performance optimization across AI compute components like NPU cores, CPUs, and high-speed interfaces.
Design and optimize signal/power integrity for AI hardware, running EM/circuit/system simulations and guiding chiplet/3D-IC layouts to ensure robust AI-native compute.
Designs AI-native SoC architectures and RTL for high-performance, energy-efficient AI compute hardware, collaborating with verification, physical implementation, and silicon bring-up teams to ensure optimal performance and manufacturability.
Leads AI hardware system PCB design, including schematic capture, layout, and SI/PI consulting for FuriosaAI’s AI-native compute platform.
Designs and executes verification strategies for AI hardware, ensuring functional correctness and coverage of block/system-level designs using SystemVerilog/UVM and Python-based tools.
Designs and optimizes AI hardware architectures, focusing on performance, power, and area (PPA) metrics. Uses Verilog, EDA tools, and scripting to perform synthesis, equivalence checking, and timing analysis for chip-level designs.
Hardware Design Verification Engineer at FuriosaAI responsible for defining and implementing verification plans, building test benches, and debugging design failures using SystemVerilog/UVM methodologies and EDA tools.
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