FuriosaAI

Hardware - Silicon Validation Team Lead (NPU SoC)

Open 65d APACLead

AI Automation Bash CI/CD C++ +10 skills

Leads silicon validation for NPU SoC chips, ensuring system-level functionality from first silicon bring-up to performance optimization and stability. Bridges hardware (RTL/DV) and software (firmware/OS) teams with structured validation processes, debugging, and test automation.

Hardware - Silicon Validation Engineer (NPU SoC)

AI Automation Bash CI/CD C++ +10 skills

Validates NPU SoC hardware for FuriosaAI, ensuring first-silicon bring-up, system-level debugging, and performance optimization across AI compute components like NPU cores, CPUs, and high-speed interfaces.

Hardware - Signal/Power Integrity Engineer (On-/Off-Chip)

AI Ethernet Oscilloscope PCIe

Design and optimize signal/power integrity for AI hardware, running EM/circuit/system simulations and guiding chiplet/3D-IC layouts to ensure robust AI-native compute.

Hardware - Senior SoC Design Engineer

Open 65d APACSenior

Designs AI-native SoC architectures and RTL for high-performance, energy-efficient AI compute hardware, collaborating with verification, physical implementation, and silicon bring-up teams to ensure optimal performance and manufacturability.

AI Automation FPGA Rtl

Hardware - Senior HW System Engineer

Open 65d APACSenior

Leads AI hardware system PCB design, including schematic capture, layout, and SI/PI consulting for FuriosaAI’s AI-native compute platform.

AI Pcb

Hardware - Senior Design Verification Engineer

Open 65d APACSenior

AI Automation Bash Ethernet PCIe +4 skills

Designs and executes verification strategies for AI hardware, ensuring functional correctness and coverage of block/system-level designs using SystemVerilog/UVM and Python-based tools.

Hardware - Physical Engineering (PI/PD) Engineer

AI Asic Bash Ethernet PCIe +2 skills

Designs and optimizes AI hardware architectures, focusing on performance, power, and area (PPA) metrics. Uses Verilog, EDA tools, and scripting to perform synthesis, equivalence checking, and timing analysis for chip-level designs.

Hardware - Design Verification Engineer

AI Bash PCIe Perl Python +3 skills

Hardware Design Verification Engineer at FuriosaAI responsible for defining and implementing verification plans, building test benches, and debugging design failures using SystemVerilog/UVM methodologies and EDA tools.

Hardware - AI Chip Architect

AI C++ Machine Learning Rtl Verilog

Designs AI-native hardware architectures and RTL implementations for high-performance, energy-efficient AI chips, focusing on chip modules, simulation, and optimization for power, timing, and area.