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Senior Design Verification Engineer (Unit Level Test)
APACSenior
Taiwan
Zhubei City, Hsinchu CountyThe Role: As a Design Verification Engineer, you will work with CPU designers, compiler team, performance team, and system verification team to generate the test cases automatically to fit those teams verification…
C++ Uvm
3 views last week
Design Verification Engineer to Staff Engineer (Unit Level Test)
APACStaff
Taiwan
Zhubei City, Hsinchu CountyThe Role: As a Design Verification Engineer, you will work with CPU designers, compiler team, performance team, and system verification team to generate the test cases automatically to fit those teams verification…
C++ Uvm
2 views last week
Senior Design Verification Engineer
APACSenior
Taiwan
Zhubei City, Hsinchu CountyThe Role: As a Design Verification Engineer, you will work with CPU designers, compiler team, performance team, and system verification team to generate the test cases automatically to fit those teams' verification…
C++ Python SystemVerilog