Ports ASIC RTL designs onto FPGA prototypes for pre-silicon emulation: refactoring clock/memory/analog blocks, running synthesis, place-and-route and timing closure in Xilinx Vivado, Intel Quartus or Synopsys ProtoCompiler, performing SpyGlass CDC sign-off, and bringing up boards with JTAG/logic analyzers while integrating PCIe, AXI, Ethernet and DDR interfaces.
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