FPGA Engineer - ASIC Prototyping & Emulation
Summary
Ports ASIC RTL designs onto FPGA prototypes for pre-silicon emulation: refactoring clock/memory/analog blocks, running synthesis, place-and-route and timing closure in Xilinx Vivado, Intel Quartus or Synopsys ProtoCompiler, performing SpyGlass CDC sign-off, and bringing up boards with JTAG/logic analyzers while integrating PCIe, AXI, Ethernet and DDR interfaces.
Key Responsibilities
ASIC-to-FPGA RTL Porting & Refactoring: Convert ASIC RTL logic for FPGA/HAPS targets, including gated clock trees to clock enables/MMCMs, ASIC memory macro wrappers to FPGA BRAM/UltraRAM, and analog block stubbing.
FPGA Implementation & Synthesis: Drive complete synthesis, place-and-route, physical floorplanning, and bitstream generation using Xilinx Vivado, Intel Quartus Prime, or Synopsys ProtoCompiler.
Timing Closure & CDC Sign-off: Perform Static Timing Analysis (STA), apply timing constraints (XDC/SDC), execute SpyGlass Lint/CDC/RDC checks, and resolve critical-path violations.
Hardware Bring-Up & In-System Debug: Conduct physical board bring-up using JTAG, Vivado ILA, or ChipScope logic analyzers to debug real-time hardware issues.
Protocol & IP Integration: Integrate high-speed interfaces and bus protocols including PCIe, AMBA AXI4/AHB, Ethernet MAC/PHY, DDR/LPDDR, I2C, SPI, and UART.
Education: B.Tech / M.Tech in ECE, EEE, VLSI Design, or Embedded Systems.
Experience: 5+ years of hands-on experience in FPGA design and pre-silicon ASIC prototyping.
Core Expertise: Must possess direct, hands-on experience in converting ASIC RTL logic to FPGA targets (candidates with purely native FPGA design, board testing, or verification-only backgrounds will not be considered).
Tools: Xilinx Vivado, Intel Quartus Prime, Synopsys ProtoCompiler / HAPS, SpyGlass Lint/CDC, Verdi, QuestaSim/ModelSim.
Languages: Verilog, SystemVerilog, VHDL, and scripting in TCL or Python
