Advanced R&D - Digital Design Engineer

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Job title: Advanced R&D - Digital Design Engineer

Location : Lausanne, Switzerland

The Digital Design Engineer designs and implements the digital sub-systems of our high-speed communication IPs — background calibration engines, adaptation loops, DSP kernels, FEC blocks, and control state machines — in advanced FinFET nodes. You will bridge system-level algorithms and mixed-signal front-ends, owning RTL through synthesis, timing closure, and low-power sign-off.

Immediate key objective

• Deliver production-quality RTL for one or more digital blocks (e.g., FEC encoder/decoder, BER-based background calibration engine, phase-interpolator control) meeting timing, area, and power targets.

• Drive DFT integration and closure for your blocks, working with the physical design team.

• Support silicon bring-up by developing firmware-level test sequences and closing the loop with characterization data.

Responsibility

• Own RTL design, synthesis, timing closure, and functional verification of assigned digital blocks.

• Define block-level architecture in collaboration with system architects and analog designers.

• Integrate blocks with DFT, low-power, and physical design flows.

• Support post-silicon bring-up, debug, validation, and productization.

• Contribute to the analysis and implementation of communication algorithms (modulation, calibration, encoding/decoding, FEC).

• Produce clear design, verification, and progress reports.

Required Experience

• 5+ years designing high-speed, power-efficient digital systems for wireline or wireless communications.

• Strong technical background in high-speed digital architectures and circuits in deep-submicron CMOS/FinFET.

• Proven experience with industry-standard synthesis, timing, and verification flows.

• Solid foundation in signal processing.

• Hands-on experience with low-power design techniques: clock gating, multi-VDD, UPF.

• CDC/RDC analysis and clock-architecture experience for high-speed sub-systems.

• Prior FEC (Reed-Solomon, LDPC) or adaptation-loop RTL implementation.

Required Skills

• Strong RTL coding (SystemVerilog), synthesis, and static timing analysis.

• Proficient with DFT insertion (scan, MBIST, JTAG) and DFM awareness.

• Hands-on with Cadence/Synopsys implementation and verification flows (Genus/Innovus or DC/ICC2, Xcelium/VCS, Spyglass, PrimeTime).

• Strong scripting (Python preferred) for design automation, tool setup, and data analysis.

• Analytical skills to translate system-level requirements into digital architectures.

• Self-motivated with strong sense of ownership; effective communicator and team player.

Required Education

• Proven experience and/or Masters or Ph.D. in E.E., Communications or other relevant fields

• MSc in electronics/electrical engineering (equivalent or higher)