<Automotive>SOC chip design for DFT/DFM

The successful candidate will be responsible for DFT and DFM methodologies, design, and implementation for system-on-chip (SoC) designs.
The candidate will also collaborate with the design and layout teams to integrate DFT/DFM requirements.

• SoC testing architecture design
• Support project NPI(new product introduction) to MP(mass production) (test program development, coverage enhancement, yield improvement, cost reduction)
• Cowork w/ IP, test engineer, process team, board design to fulfill CP/FT/SLT test requirement.

#LI-LL1

Required Industry Experience:

• Minimum of 3+ years of proven experience in DFT/DFM in SoC chip design .
• Experience in semiconductor manufacturing process, reliability, and yield improvement.

Key Technology Skills:

• Strong knowledge of SCAN, MBIST, BIST...DFT design structure and test coverage enhancement.
• Strong knowledge of manufacture(DFM) yield improvement, test time reduction, test cost reduction.
• Knowledge of SoC design tools and methodologies, including synthesis, static timing analysis, and formal verification.
• Skilled in RTL coding and scripting languages, such as TCL/Perl/Python.

Nice to have:

• Strong knowledge of automated testing equipment (ATE) and test program development.
• Expertise in EDA tools for DFT analysis, such as Mentor Graphics Tessent or Synopsys DFTMAX, Tessent MBIST, automotive LBIST.
• Expertise in ATPG pattern generation and coverage analysis for SoC chip design.
• Experience in high performance and low power design methodologies.