Custom Circuit Design (Sr. Staff / Principal)
Summary
Leads the design and optimization of high-performance, low-power standard cell libraries and custom digital circuits, including transistor-level innovation, arithmetic block architecture, and circuit verification across PVT corners. Focuses on reliability sign-off, low-power innovations, and mentoring engineers in advanced CMOS technologies.
Velaura seeks a Sr. Staff/Principal Custom Circuit Design Engineer to lead high-performance, low-power standard-cell libraries and custom digital circuits across advanced process technologies. The role covers transistor-level innovation, arithmetic circuits, verification, reliability sign-off, methodology improvements, cross-functional collaboration, and mentoring.
Responsibilities
- Lead standard-cell architecture, design, and optimization for performance, power, and area.
- Design and optimize transistor-level sequential and combinational circuits.
- Architect arithmetic building blocks including adders, multipliers, and integer and floating-point MAC units.
- Develop schematics in Cadence Virtuoso and perform parasitic extraction using StarRC or Quantus.
- Verify circuits across PVT corners using HSPICE, PrimeSim XA, or Spectre.
- Drive Monte Carlo statistical verification and variation analysis.
- Own reliability sign-off including electromigration, IR-drop, self-heating, aging, ESD, and latch-up robustness.
- Drive low-power circuit innovations and power-intent-aware methodologies.
- Collaborate with layout, characterization, physical design, CAD, STA, and product engineering teams.
- Improve design methodologies, automation, and technical best practices.
- Mentor engineers and provide technical leadership.
Requirements
- 10+ years of experience in custom digital circuit design, standard-cell development, or memory circuit design.
- Expertise in transistor-level CMOS design for advanced technology nodes.
- Experience designing and optimizing high-performance, low-power standard-cell libraries.
- Understanding of FinFET and Gate-All-Around technologies.
- Experience with HSPICE, PrimeSim XA, or Spectre.
- Experience with StarRC or Quantus parasitic extraction.
- Knowledge of statistical verification, Monte Carlo analysis, and variation-aware design.
- Experience with reliability verification including EM, IR-drop, aging, and self-heating.
- Master's or Ph.D. in Electrical Engineering, Electronics Engineering, or a related discipline preferred.
- Experience with Python, Tcl, or Perl automation preferred.
Benefits
- Performance-based incentives
- Equity participation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements
- Professional development opportunities