<Data center>Mixed-Signal Digital IC Design Engineer(Serdes, HS Interface)
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Description
1. Serdes/High speed interface related PHYD IP architecture planning
2. Serdes/High speed interface related PHYD IP RTL coding
3. Serdes/High speed interface related PHYD IP front-end and back-end integration
4. Co-work with PCS/MAC design team and DV team for IP verification
5. Co-work with Analog design team for PHY co-simulation
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