Design and Verification Engineer

Roles and Responsibilities :

• Design and develop verification environments using SystemVerilog, UVM, and Python.
• Develop testbenches to verify complex digital designs using C++ and emulators.
• Collaborate with cross-functional teams to identify requirements and create test plans.
• Analyze results, debug issues, and provide technical documentation.

Job Requirements :

• 5-8 years of experience in Design & Verification Engineering.
• Strong knowledge of System Verilog, UVM, Python programming languages.
• Experience with C++, Emulators (e.g., VCS), Testbench development.