Design and Verification Engineer
Posted
Summary
ASIC Design Verification engineer building UVM testbenches and driving IP/sub-system/SoC verification closure for Ethernet and high-speed networking data-center ASICs. Day to day: simulation, formal verification and emulation, coverage closure, debugging failures with design teams. Core stack: SystemVerilog, UVM, Verilog, AXI/APB, Python/C/C++.
We are hiring experienced ASIC Design Verification (DV) Engineers with expertise in Ethernet and high-speed networking protocols. The role involves IP/Sub-System/SoC verification, UVM-based verification environment development, verification closure, debugging, and collaboration with cross-functional ASIC design teams to deliver first-pass silicon success for data center applications.
Key Responsibilities
- Develop and execute IP/Sub-System/SoC verification plans.
- Build UVM-based verification environments and functional test cases.
- Perform simulation, formal verification, and emulation for verification closure.
- Debug functional failures and work closely with ASIC Design teams.
- Drive functional and code coverage to achieve verification closure.
- Collaborate with Design, Emulation, Silicon Validation, and Software teams.
- Mentor engineers and contribute to verification methodology improvements.
Mandatory Skills
- 5-10 years of ASIC Design Verification experience.
- Strong hands-on experience in SystemVerilog, Verilog, UVM.
- Experience with AMBA AXI/APB protocols.
- Strong expertise in at least one high-speed protocol: Ethernet (Mandatory), PCIe, RDMA.
- Experience in IP, Cluster, Sub-System, or SoC Verification.
- Hands-on experience with Python/C/C++ for verification.
- Experience in verification planning, testbench development, debugging, functional & code coverage.
- Strong knowledge of networking/data-center ASICs.
Preferred Skills
- UVM environment development from scratch.
- Formal Verification, SV Assertions, Emulation.
- Verification of ARM/RISC-V based SoCs.
- High-speed interface verification (Ethernet, PCIe, DDR, HBM).
- Experience with Git/SVN/Mercurial, waveform debugging tools, and automation scripting (Python/Perl/TCL).
Education
- Bachelor's degree in Computer Science, Electronics, Computer Engineering, or a related technical field.
Keywords
ASIC Design Verification, ASIC DV, SystemVerilog, UVM, Verilog, Ethernet, PCIe, RDMA, AXI, APB, SoC Verification, IP Verification, Networking, RTL Verification, Functional Verification, Python, C++, ARM, RISC-V, Emulation, Formal Verification, Data Center ASIC.
Note
Note: Candidates with more than 30 days' notice period will not be considered.