Design Verification Engineer
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Summary
Design Verification Engineer developing verification strategies, testbenches, and coverage plans for AI hardware. Day-to-day involves implementing tests, debugging across simulation and silicon bring-up, and improving infrastructure using SystemVerilog, UVM, and Python.
You will develop verification strategies, tests, coverage plans, and reusable environments based on microarchitecture. You will implement and debug tests, manage regressions and coverage, analyze issues across simulation, emulation, and silicon bring-up, and improve verification infrastructure and methodologies.
Responsibilities
- Develop verification strategies, detailed tests, and coverage plans based on microarchitecture
- Create reusable verification environments with stimulus, checkers, assertions, and coverage
- Implement tests, manage regressions, gather coverage, and debug test failures
- Collaborate with architecture, RTL design, physical design, firmware, and validation teams
- Analyze and debug issues across simulation, emulation, and silicon bring-up
- Improve verification infrastructure, flows, methodologies, and best practices
Requirements
- Knowledge of SystemVerilog testbenches, DPI, and UVM
- Programming skills and knowledge of software engineering practices and object-oriented design
- Experience developing scalable and portable testbenches and components
- Experience with verification methodologies and tools, including simulators, waveform viewers, automation, coverage collection, and gate-level simulations
- Proficiency in Python or Perl
- 3–5+ years of design verification experience