Digital IC Design Engineer/Senior(台北)

1. Participate in ASIC/SoC digital architecture and micro-architecture definition, RTL design (Verilog/SystemVerilog), and functional implementation.
2. Develop high-quality RTL for PCIe or other high-speed interface IPs and support testbench/BFM bring-up and functional verification when needed.
3. Collaborate with verification engineers to define verification scope, review test plans, and debug simulation or functional issues.
4. Perform RTL lint, CDC/RDC, reset, and timing-related design checks; support synthesis, DFT, backend integration, and ECO activities.
5. Analyze and resolve design issues during simulation, FPGA prototyping, emulation, silicon validation, and system integration.
6. Collaborate with architecture, firmware, physical design, verification, and validation teams throughout the full chip development cycle.
7. Prepare and maintain design specifications, micro-architecture documents, and implementation documentation to ensure design quality and traceability.

1. 參與 ASIC／SoC 數位架構與 Micro-architecture 規劃，負責 RTL 設計（Verilog／SystemVerilog）與功能實作。
2. 開發 PCIe 或其他高速介面 IP RTL，並於需要時支援 Testbench／BFM 建置及基本功能驗證。
3. 與 Verification 團隊合作，定義驗證範圍、審查測試計畫，並協助模擬及功能除錯。
4. 執行 RTL Lint、CDC／RDC、Reset 與 Timing 檢查，並支援 Synthesis、DFT、Backend Integration 與 ECO。
5. 分析並解決 Simulation、FPGA Prototype、Emulation、Silicon Validation 及系統整合階段的設計問題。
6. 與 Architecture、Firmware、Physical Design、Verification 及 Validation 團隊跨部門合作，完成晶片開發。
7. 撰寫並維護設計規格、Micro-architecture 文件及實作文件，確保設計品質與可追溯性。