Digital IC Verification Engineer (Junior / Entry-Level)
Summary
Junior IC verification engineer builds and runs testbenches in SystemVerilog/UVM to validate DSP and datapath RTL against specs, debug failures, and automate regression workflows.
About the Role
Weare seeking a motivated Junior Digital IC Verification Engineer to join our design verification (DV) team. In this role, you will be responsible for verifying high-speed DSP and digital logic blocks used in optical communication systems. You will work closely with RTL designers, architects, and system teams to ensure functional correctness and robustness of ASIC/SoC designs for next-generation optical interconnects.
Key Responsibilities:
· Develop and maintain testbenches using SystemVerilog and UVM for block-level and subsystem-level verification.
· Verify RTL designs for DSP blocks, datapaths, and control logic against specifications.
· Create constrained-random stimulus, directed tests, and functional coverage models.
· Debug failing simulations and perform root cause analysis with RTL engineers.
· Assist in defining verification plans, strategies, and coverage goals.
· Verify high-throughput and latency-sensitive datapath designs for ODSP systems.
· Collaborate with RTL, system, DSP, and physical design teams.
· Develop scripts to automate regression, testing, and data analysis.
Requirements:
· Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related fields.
· 0–2 years of experience in digital IC verification or RTL design (fresh graduates welcome).
· Strong fundamentals in digital design and verification concepts.
· Basic understanding of ASIC/SoC design and verification flow.