Digital Implementation Engineer (STA)

Base: Central Singapore

Key Responsibilities:

• Develop, maintain, and optimize flows for logic synthesis, formal verification, and STA, ensuring quality, accuracy, and efficiency.
• Develop and review module-level and full-chip SDC timing constraints with front-end design teams.
• Execute full-chip STA, identify timing issues, and drive timing closure.
• Implement timing ECOs and collaborate with front-end and back-end teams to resolve timing-related issues.

Requirements:

• Bachelor’s degree or above in Electronic Information Engineering, Microelectronics, IC Engineering, AI, or a related field.
• Strong Verilog and SDC skills, with a solid understanding of synthesis, formal verification, STA, and timing closure.
• Hands-on experience with EDA tools for synthesis, formal verification, and STA.
• Proficiency in Tcl, Perl, and Python; strong flow automation skills are a plus.
• Experience with formal verification debugging, timing ECOs, and full-chip STA is preferred.
• Familiarity with DFT, including BIST, SCAN, JTAG, and ATPG, is a plus.
• Strong analytical, problem-solving, communication, and teamwork skills, with a proactive and ownership-driven mindset.

EA License: R1987104