DV Engineers (Ethernet)

Roles and Responsibilities :

• Design, develop, test, and verify Ethernet-based IP blocks using SystemVerilog and UVM.
• Collaborate with cross-functional teams to integrate ASIC designs into larger systems.
• Develop and maintain reusable verification components (e.g., functions, modules) for efficient testing of complex digital circuits.
• Troubleshoot issues related to Ethernet protocol implementation in both software and hardware environments.

Job Requirements :

• 5-10 years of experience in ASIC verification using languages such as SystemVerilog and Python.
• Strong understanding of ARM architecture and RISC instruction set.
• Experience with emulators like QEMU or similar tools is required; knowledge of Arm simulators is an added advantage.