Experienced Verification Engineer - System IP
Posted Updated
- Contribution to System IP microarchitecture specification and design
- Contribution to verification, modelling and debug using SystemVerilog, C and C++
- Proposition and prototyping of new methodologies for efficiency
- Ownership and development of verification plans and environments
- Collaboration with engineers across design, performance modelling, validation, and implementation to meet functional, performance, power and area goals
- Master’s degree in Electrical Engineering or Computer Engineering or Bachelor's degree with related experience
- Experience in object oriented software development (C++ or SystemVerilog)
- Interest in and theoretical knowledge of digital circuits, FPGAs, embedded software (C)
- Enthusiasm and curiosity to learn new things and ways
- Post-degree work experience
- Exposure to all stages of the product development cycle: concept, specification, implementation, testing, documentation, release and support
- Experience with block level RTL design and verification of non-trivial ASIC or FPGA developments; SystemVerilog preferred
- Scripting skills such as Linux, Bash, Python
- Ability to travel occasionally for training and customer meetings
- Proficiency in both written and oral English
- Competitive salary within the range HUF 21,250,000 - HUF 28,750,000 per year
- Support for visa sponsorship costs for the employee
- Hybrid working environment supporting high performance and personal wellbeing
- Health and wellness benefits
- Work and life success support
- Financial rewards beyond salary
- Professional and personal development opportunities
- Supportive community environment