FAE - Data Center Networking & Security

We are seeking a technically strong, customer-oriented FAE to support Lattice FPGA solutions for hyperscale data center networking and security. In this role you will engage directly with a strategic ODM/JDM account and its downstream customers to enable successful design-in and deployment of Lattice FPGAs on high-speed Ethernet switch platforms.

Key Responsibilities:
1. Support customers throughout the design cycle for data center switch platforms, from architecture definition through mass production.
2. Enable platform-security designs: PFR, immutable hardware Root of Trust, secure boot, runtime protection (SPI flash and I2C monitoring, BMC SPI upgrade monitoring), and secure firmware update.
3. Support security attestation and provisioning: SPDM attestation (MCTP over I2C/I3C, PCIe DOE), device identity and certificates, HSM signing, and secure manufacturing provisioning.
4. Guide high-speed switch-platform bring-up: switch board and baseboard, COMe/BMC, switch-ASIC and PCIe-switch protection, and board-level integration.
5. Drive design-in of Lattice security devices (MachXO family, XO3D, and XO5D / LFMXO5-55TDQ) as the common security/PFR platform across the customer's switch portfolio.
6. Guide customers through the Lattice design flow using Radiant, Diamond, Propel and etc..
7. Deliver technical presentations, training, and workshops (e.g., LTPI, MP-ESTI, security / root-of-trust, and PFR solutions).
8. Troubleshoot timing closure, simulation, signal-integrity, and board-level integration issues in high-speed networking systems.
9. Coordinate support across the customer's global design sites (e.g., Shanghai, Dongguan, Penang) and software teams, managing multiple concurrent programs on tight schedules.
10. Provide feedback to product and R&D teams on customer requirements and emerging networking and security trends (PQC, CNSA 2.0, OCP Security).

Job Requirements:
1. Bachelor's or Master's degree in EE or a related field.
2. 3-5 years of FPGA development, technical support, or FAE experience.
3. Strong hands-on experience with data center networking and high-speed Ethernet switching platforms (e.g., 800G / 1.6T / 3.2T switches).
4. Familiarity with data center switch-ASIC platforms (e.g., Broadcom Tomahawk-class TH6 / TH7) and switch / line-card board architecture.
5. Understanding of co-packaged optics and high-speed serial signal integrity is a strong plus.
6. Experience with switch platform management and control-plane interfaces: PCIe and PCIe switching, MCTP, SMBus / I2C / I3C, SGPIO, eSPI, and LTPI.
7. Exposure to whitebox / open networking and OCP hardware ecosystems.
8. Hands-on FPGA design flow: RTL (Verilog / VHDL / SystemVerilog), synthesis, simulation, and debugging.
9. Strong knowledge of Lattice toolchains (Radiant, Diamond, Propel etc.) and Lattice security FPGAs (XO3D and XO5D / MachXO family).
10. Solid understanding of platform-security concepts: PFR (NIST SP800-193), hardware root of trust, secure boot, cryptography (SHA-2/3, ECC, RSA, AES-256, TRNG), key / OTP management, and SPDM attestation.
11. Familiarity with BMC / BIOS security ecosystems: OpenBMC / AMI BMC, AMI Tektagon, BIOS, and standard interfaces (I2C, SPI, eSPI, SGPIO, LTPI).
12. Awareness of post-quantum cryptography (ML-KEM / ML-DSA), CNSA 2.0, FIPS 140-3, and OCP Security / OCP SAFE is a plus.
13. Lab skills with oscilloscopes, logic analyzers, protocol analyzers, and FPGA prototyping boards.
14. Experience with CPU / XPU and general-purpose server platform design (plus).
15. Familiarity with embedded systems and SW integration (FPGA, processors, and interfaces).
16. Excellent problem-solving and debugging skills.
17. Strong presentation and communication skills to engage customers and their global design teams effectively.
18. Ability to work cross-functionally and manage multiple concurrent customer programs under tight schedules.
19. Willingness to travel and provide on-site support across regional design centers.